公开(公告)号：US20230326758A1

公开(公告)日：2023-10-12

申请号：US18040927

申请日：2021-01-27

申请人： Mitsubishi Electric Corporation

发明人： Koichiro NISHIZAWA ,  Daisuke TSUNAMI

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L29/47 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/288

CPC分类号： H01L21/288 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/30612 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66878

摘要： A substrate (1) having a GaN surface (2) is immersed in a catalyst metal solution (4) containing potassium hydroxide and a plating catalyst metal salt while being irradiated with ultraviolet light to deposit a catalyst metal (5) on the GaN surface (2). A metal film (7) is formed on the GaN surface (2) having the catalyst metal (5) deposited thereon by electroless plating.

公开(公告)号：US20140264445A1

公开(公告)日：2014-09-18

申请号：US13927580

申请日：2013-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ying Xiao

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66636 ,  H01L29/0653 ,  H01L29/26 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/66878 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.

摘要翻译： 本公开涉及一种半导体器件。 用于场效应晶体管的示例性结构包括：基底，其包括主表面和主表面下方的空腔; 在基板的主表面上的栅极堆叠; 邻接栅堆叠的一侧的间隔件; 设置在所述栅极堆叠侧的浅沟槽隔离（STI）区域，其中所述STI区域在所述衬底内; 以及分布在栅极堆叠和STI区域之间的源极/漏极（S / D）结构，其中S / D结构包括空腔中的应变材料，其中应变材料的晶格常数不同于晶体常数 基质; 以及设置在所述基板和应变材料之间的S / D延伸部，其中所述S / D延伸部包括在所述间隔件下方延伸并且基本垂直于所述主表面的部分。

公开(公告)号：US20070155072A1

公开(公告)日：2007-07-05

申请号：US11327257

申请日：2006-01-05

申请人： Thomas Winslow

发明人： Thomas Winslow

IPC分类号： H01L21/338

CPC分类号： H01L29/812 ,  H01L29/0646 ,  H01L29/1029 ,  H01L29/1075 ,  H01L29/66848 ,  H01L29/66878

摘要： A MESFET and method for fabricating a MESFET are provided. The method includes forming an n-type channel portion in a substrate and forming a p-type channel portion in the substrate. A boundary of the n-type channel portion and a boundary of the p-type channel portion define an intrinsic region in the substrate.

摘要翻译： 提供了一种用于制造MESFET的MESFET和方法。 该方法包括在衬底中形成n型沟道部分并在衬底中形成p型沟道部分。 n型沟道部分的边界和p型沟道部分的边界限定衬底中的本征区域。

公开(公告)号：US20040175853A1

公开(公告)日：2004-09-09

申请号：US10785944

申请日：2004-02-26

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kaoru Inoue ,  Yoshito Ikeda ,  Yutaka Hirose ,  Katsunori Nishii

IPC分类号： H01L021/76 ,  H01L021/00

CPC分类号： H01L29/66878 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/8126

摘要： A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

摘要翻译： 半导体器件具有由III-V族氮化物半导体和欧姆电极构成的有源区和形成在有源区上的栅电极。 有源区域的整个表面暴露于等离子体，使得其中的电子的表面电位低于整个表面不暴露于等离子体的情况。

公开(公告)号：US6037200A

公开(公告)日：2000-03-14

申请号：US39395

申请日：1998-03-16

申请人： Tomoya Uda ,  Akiyoshi Tamura

发明人： Tomoya Uda ,  Akiyoshi Tamura

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/338 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/66878 ,  H01L21/28581 ,  H01L21/28593 ,  H01L29/0891 ,  H01L29/42316 ,  H01L21/2654 ,  H01L21/26586

摘要： A WSi film is deposited on a semi-insulative GaAs substrate. Thereafter, a first Al mask and a second SiO.sub.2 mask are formed such that these two masks overlap on the WSi film. A SF.sub.6 /CF.sub.4 mixture, which contains a gas of SF.sub.6 in an amount of more than 20%, is used to dry-etch the WSi film. The WSi film is T-shaped, in other words the WSi film becomes gradually downwardly narrower in lateral length. The second mask is stripped. A .GAMMA.-shaped gate electrode is formed by means of an anisotropic etching process. Subsequently, an isotropic etching process is carried out to reduce the gate length of the electrode down to 0.5 .mu.m or less. Silicon ions are implanted to form individual n' layers. A through film is deposited. Silicon ions are implanted to form individual n.sup.+ layers.

摘要翻译： WSi膜沉积在半绝缘GaAs衬底上。 此后，形成第一Al掩模和第二SiO 2掩模，使得这两个掩模在WSi膜上重叠。 使用含有大于20％的SF 6的气体的SF 6 / CF 4混合物来干法蚀刻WSi膜。 WSi膜是T形的，换句话说，WSi膜在横向长度上逐渐变窄。 第二个面具被剥去。 通过各向异性蚀刻工艺形成GAMMA形栅电极。 随后，进行各向同性蚀刻处理以将电极的栅极长度减小到0.5μm或更小。 植入硅离子以形成单独的n'层。 通过膜被沉积。 植入硅离子以形成单独的n +层。

公开(公告)号：US5904554A

公开(公告)日：1999-05-18

申请号：US979862

申请日：1997-11-26

申请人： Chihiro Uchibori ,  Masanori Murakami ,  Akira Otsuki ,  Takeo Oku ,  Masaru Wada

发明人： Chihiro Uchibori ,  Masanori Murakami ,  Akira Otsuki ,  Takeo Oku ,  Masaru Wada

IPC分类号： H01L21/28 ,  H01L21/203 ,  H01L21/265 ,  H01L21/285 ,  H01L21/337 ,  H01L21/338 ,  H01L29/08 ,  H01L29/45

CPC分类号： H01L29/66924 ,  H01L21/28575 ,  H01L21/28581 ,  H01L29/0891 ,  H01L29/452 ,  H01L29/66878

摘要： An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n.sup.+ -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300.degree. C. for 30 minutes and next at, e.g. 650.degree. C. for one second to fabricate an ohmic electrode.

摘要翻译： 公开了具有实际令人满意的特性的诸如GaAs半导体的III-V族化合物半导体的欧姆电极。 通过溅射等将非单晶InAs层，Ni膜，WSi膜和W膜依次沉积在n +型GaAs衬底上，随后通过剥离等进行图案化，以制造用于制造的多层结构 欧姆电极。 然后首先将结构退火，例如。 300℃，30分钟，然后在例如 650℃下制造欧姆电极1秒钟。

公开(公告)号：US5532505A

公开(公告)日：1996-07-02

申请号：US150349

申请日：1993-11-10

申请人： Nobuhiro Kuwata

发明人： Nobuhiro Kuwata

IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L29/36 ,  H01L29/812

CPC分类号： H01L29/66878 ,  H01L29/1029 ,  H01L29/812 ,  H01L29/365

摘要： This invention aims at providing an high output FET having a planar type-gate structure suitable for integration, and a structure that suppresses long gate effect. A heavily doped thin channel layer 13 is formed on a semiconductor substrate 11, and a cap layer including a doped layer 15 is formed on the channel layer 13. A thickness and a dopant concentration of the doped layer 15 are so set that the doped layer 15 per se is depleted by a surface depletion region resulting from an interface level of the semiconductor substrate surface, and the surface depletion region does not widen to the channel layer 13. Consequently no long gate effect takes place on the side where a gate bias is lower.

摘要翻译： 本发明的目的在于提供一种具有适于集成的平面型栅极结构的高输出FET和抑制长栅极效应的结构。 在半导体衬底11上形成重掺杂的薄沟道层13，并且在沟道层13上形成包括掺杂层15的覆盖层。掺杂层15的厚度和掺杂剂浓度被设定为使掺杂层 15本身由由半导体衬底表面的界面水平产生的表面耗尽区耗尽，并且表面耗尽区域不会扩大到沟道层13.因此，在栅极偏置的一侧不发生长的栅极效应 降低。

公开(公告)号：US5510280A

公开(公告)日：1996-04-23

申请号：US74355

申请日：1993-06-10

申请人： Minoru Noda

发明人： Minoru Noda

IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/336 ,  H01L21/338 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/66878 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/66659

摘要： A field effect transistor having an asymmetric gate includes high dopant concentration source and drain regions. The drain region is shallower and of lower dopant concentration than the source region. The drain is spaced from the gate electrode. Therefore, an ideal FET having a reduced short channel effect and having a lower source resistance and high current drivability (gm) is obtained. When the drain region is produced by ion implantation through a film and the source region is produced by the implantation directly into the substrate, only the drain region is separated from the gate. When the insulating film on the source region is separated from the insulating film on the drain region, the insulating film on the source region is reliably selectively removed, whereby high controllability is obtained.

摘要翻译： 具有不对称栅极的场效应晶体管包括高掺杂浓度源极和漏极区域。 漏极区域比源区域更浅，掺杂浓度低。 漏极与栅电极间隔开。 因此，获得了具有降低的短沟道效应并且具有较低源极电阻和高电流驱动能力（gm）的理想FET。 当通过离子注入通过膜产生漏极区域并且通过直接注入到衬底中产生源极区域时，只有漏极区域与栅极分离。 当源极区域上的绝缘膜与漏极区域上的绝缘膜分离时，源极区域上的绝缘膜被可靠地选择性地去除，从而获得高可控性。

公开(公告)号：US5341015A

公开(公告)日：1994-08-23

申请号：US625798

申请日：1990-12-11

申请人： Yasutaka Kohno

发明人： Yasutaka Kohno

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/318 ,  H01L21/338 ,  H01L23/52 ,  H01L29/47 ,  H01L29/812 ,  H01L29/80 ,  H01L29/04 ,  H01L29/84

CPC分类号： H01L29/66878 ,  H01L29/47 ,  H01L2224/48091

摘要： In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the vector sum of the stress in the gate metal and the stress produced by the insulating film on the gate electrode is zero. A production method of a semiconductor device includes producing a gate electrode having the same but opposite stress of an insulating film by sputtering under an adjusted gas pressure a target of WSi.sub.x and depositing an insulating film covering the gate electrode.

摘要翻译： 在具有覆盖化合物半导体衬底上的栅电极的栅电极和绝缘膜的半导体器件中，栅极金属中的应力的矢量和由栅电极上的绝缘膜产生的应力为零。 半导体器件的制造方法包括通过在调整后的气压下通过溅射在WSix上制造具有与绝缘膜相同但相反的应力的栅电极，并沉积覆盖栅电极的绝缘膜。

公开(公告)号：US5322806A

公开(公告)日：1994-06-21

申请号：US393950

申请日：1989-08-15

申请人： Yasutaka Kohno ,  Masayuki Sakai

发明人： Yasutaka Kohno ,  Masayuki Sakai

IPC分类号： H01L21/31 ,  H01L21/28 ,  H01L21/285 ,  H01L21/316 ,  H01L21/338 ,  H01L21/768 ,  H01L29/812 ,  H01L21/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/44

CPC分类号： H01L29/66878 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/76819

摘要： A method of producing a semiconductor device including the steps of depositing a refractory metal gate electrode at a predetermined region of a semi-insulating substrate surface, and thereafter depositing an insulating film at regions other than the gate electrode region, wherein the production of the insulating film is carried out by an electron cyclotron resonance plasma CVD method while applying a high frequency electrical bias to the substrate.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半绝缘衬底表面的预定区域沉积难熔金属栅极电极，然后在除栅电极区域之外的区域沉积绝缘膜，其中绝缘 通过电子回旋共振等离子体CVD法进行膜的同时向基板施加高频电偏压。