公开(公告)号：US06901010B1

公开(公告)日：2005-05-31

申请号：US10119366

申请日：2002-04-08

申请人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

发明人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/107 ,  G11C16/0475 ,  G11C16/3409 ,  G11C16/3445 ,  G11C2216/18

摘要： An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

摘要翻译： 位于正常和互补位置的位的多位存储器阵列中的闪存单元的擦除方法。 执行正常位置中的位的擦除验证，并且如果正常位置中的位失败，并且如果还没有达到最大擦除脉冲计数，则将擦除脉冲施加到正常位和补充位。 执行补充位置中的位的擦除验证，并且如果补充位中的位失败，并且如果还没有达到最大擦除脉冲计数，则擦除脉冲将被施加到互补位和正常位位置。 如果这些位通过擦除验证，则这些位经过软编程验证。 如果这些位过高，并且如果没有达到软编程脉冲计数，则软编程脉冲将被施加到过高位。

公开(公告)号：US06897110B1

公开(公告)日：2005-05-24

申请号：US10305750

申请日：2002-11-26

申请人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

发明人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.

摘要翻译： 一种制造存储器阵列的方法，同时保护其免受电荷损坏。 可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。 字线形成在位线之上，并且可以具有栅极区域。 接下来，在位线之上形成耦合到位线之一的第一金属区域。 形成不与第一金属区电耦合的第二金属区域。 然后，第一金属区域电耦合到第二金属区域。 通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。 为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。 此外，可以在位线和字线之间形成保险丝，以保护字线。

公开(公告)号：US07692962B2

公开(公告)日：2010-04-06

申请号：US11958557

申请日：2007-12-18

申请人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

发明人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5628 ,  Y10T29/49002

摘要： A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.

摘要翻译： 提供了一种简化状态存储器件以及形成和编程器件的多级闪存单元元件对的方法，每个元件被配置为存储空白电平或两个或更多个程序电平。 在一个实施例中，缩减状态存储器件包括被配置为在存储器单元元件对中存储包括两个空白电平，两个程序电平以及一个空白电平和一个程序电平的多个程序模式组合的一个模式组合的组件， 电平差别小于预定值。 在一个实施例中，形成存储器件的方法包括形成多级闪速存储器阵列的至少一个存储器件，每个存储器单元包括两个或多个存储器元件，每个存储器元件被配置为存储三个或更多个电平，并且排除 可存储在至少一个存储单元中的一个或多个程序模式组合。

公开(公告)号：US20090154235A1

公开(公告)日：2009-06-18

申请号：US11958557

申请日：2007-12-18

申请人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

发明人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

IPC分类号： G11C16/04 ,  H01S4/00

CPC分类号： G11C16/0475 ,  G11C11/5628 ,  Y10T29/49002

摘要： A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.

摘要翻译： 提供了一种简化状态存储器件以及形成和编程器件的多级闪存单元元件对的方法，每个元件被配置为存储空白电平或两个或更多个程序电平。 在一个实施例中，缩减状态存储器件包括被配置为在存储器单元元件对中存储包括两个空白电平，两个程序电平以及一个空白电平和一个程序电平的多个程序模式组合的一个模式组合的组件， 电平差别小于预定值。 在一个实施例中，形成存储器件的方法包括形成多级闪速存储器阵列的至少一个存储器件，每个存储器单元包括两个或多个存储器元件，每个存储器元件被配置为存储三个或更多个电平，并且排除 可存储在至少一个存储单元中的一个或多个程序模式组合。