公开(公告)号：US20100135082A1

公开(公告)日：2010-06-03

申请号：US12326388

申请日：2008-12-02

申请人： Fatima Bathul ,  Darlene Gay Hamilton ,  Guy Hadas

发明人： Fatima Bathul ,  Darlene Gay Hamilton ,  Guy Hadas

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/04 ,  G11C16/3454

摘要： Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level, and a subset of the group of cells that are below the next PV level are selected and a next program pulse is applied to the subset of cells to facilitate verifying the cells to pass the next PV level. The moving PV level process can continue until the group of memory elements is verified to pass the target PV level.

摘要翻译： 提出了采用移动程序验证级别以便于将数据编程到存储器组件中的存储器元件的系统，方法和设备。 程序组件可以采用指定数量的程序验证（PV）级别，其中第一编程脉冲被施加到所选择的存储器单元组，以便于验证单元通过第一PV电平。 PV电平可以移动到比第一PV电平更高的电荷电平的下一个PV电平，并且选择低于下一个PV电平的一组电池的子集，并施加下一个编程脉冲 到细胞的子集以便于验证细胞通过下一个PV水平。 移动光伏电平过程可以继续，直到存储元件组被验证通过目标光伏电平。

公开(公告)号：US07652919B2

公开(公告)日：2010-01-26

申请号：US11771961

申请日：2007-06-29

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Fatima Bathul ,  Ou Li

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Fatima Bathul ,  Ou Li

IPC分类号： G11C11/34

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3418 ,  G11C16/3427

摘要： The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.

摘要翻译： 所要求保护的主题提供了便于在存储器件中编程和读取多级多位存储器单元的系统和/或方法。 在多位存储器单元中，编程一个元件可以影响第二个元件。 元件的某些组合可能导致过多的互补位干扰，状态依赖的不均匀电荷损失和状态相关的程序干扰，从而降低存储器件的可靠性。 当高电荷电平被编程到第一元件中而同一存储器单元的第二元件未被编程时，这种效果可能是显着的。 可以使用额外的电荷电平对存储单元元件进行编程，以减轻这种影响。 例如，使用四个电荷电平可能的十六个不同元件组合可以被映射到使用五个电荷电平的二十五个可能元件组合的子集，避免可能产生过多的互补位干扰，状态依赖的非均匀电荷损失的元件组合， 和状态依赖程序干扰。

公开(公告)号：US07821840B2

公开(公告)日：2010-10-26

申请号：US12276604

申请日：2008-11-24

申请人： Guy Hadas ,  Darlene Gay Hamilton ,  Fatima Bathul

发明人： Guy Hadas ,  Darlene Gay Hamilton ,  Fatima Bathul

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed using learned drain voltages as initial drain voltages where drain voltage levels are varied during each program pulse to facilitate programming memory cells to respective intrinsic verify voltage levels based on respective data levels. A second programming phase is performed using ending drain voltages from the first programming phase as initial drain voltages where gate voltage levels are varied during each program pulse to facilitate programming memory cells to respective final verify voltage levels based on respective data levels.

摘要翻译： 介绍了促进存储器组件中数据的多阶段编程的系统，方法和设备。 基于预定义的程序模式，接收的数据被编程到使用多个编程阶段的存储器。 通过根据需要改变漏极电压来执行程序学习，以便于确定与用于第一编程阶段的相应数据电平相关联的与特定子组相关的相应漏极电压。 使用学习的漏极电压作为初始漏极电压来执行第一编程阶段，其中漏极电压电平在每个编程脉冲期间变化，以便于基于相应的数据电平将存储器单元编程到相应的内部验证电压电平。 使用来自第一编程阶段的结束漏极电压作为初始漏极电压来执行第二编程阶段，其中栅极电压电平在每个编程脉冲期间变化，以便于基于相应的数据电平将存储器单元编程到相应的最终验证电压电平。

公开(公告)号：US20060152974A1

公开(公告)日：2006-07-13

申请号：US11034642

申请日：2005-01-13

申请人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

发明人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5671

摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough. Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

公开(公告)号：US20050276120A1

公开(公告)日：2005-12-15

申请号：US10864947

申请日：2004-06-10

申请人： Ed Hsia ,  Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike

发明人： Ed Hsia ,  Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3413 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409

摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.

摘要翻译： 提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。 本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。 在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。 然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到对应于单元的期望的最终阈值电压值的最终数据状态。 可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。 在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

公开(公告)号：US08391070B2

公开(公告)日：2013-03-05

申请号：US12326388

申请日：2008-12-02

申请人： Fatima Bathul ,  Darlene Gay Hamilton ,  Guy Hadas

发明人： Fatima Bathul ,  Darlene Gay Hamilton ,  Guy Hadas

IPC分类号： G11C11/34

CPC分类号： G11C16/04 ,  G11C16/3454

摘要： Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level, and a subset of the group of cells that are below the next PV level are selected and a next program pulse is applied to the subset of cells to facilitate verifying the cells to pass the next PV level. The moving PV level process can continue until the group of memory elements is verified to pass the target PV level.

摘要翻译： 提出了采用移动程序验证级别以便于将数据编程到存储器组件中的存储器元件的系统，方法和设备。 程序组件可以采用指定数量的程序验证（PV）级别，其中第一编程脉冲被施加到所选择的存储器单元组，以便于验证单元通过第一PV电平。 PV电平可以移动到比第一PV电平更高的电荷电平的下一个PV电平，并且选择低于下一个PV电平的一组电池的子集，并施加下一个编程脉冲 到细胞的子集以便于验证细胞通过下一个PV水平。 移动光伏电平过程可以继续，直到存储元件组被验证通过目标光伏电平。

公开(公告)号：US07872916B2

公开(公告)日：2011-01-18

申请号：US12330928

申请日：2008-12-09

申请人： Fatima Bathul ,  Darlene Gay Hamilton ,  Michael Achter ,  Hagop Artin Nazarian

发明人： Fatima Bathul ,  Darlene Gay Hamilton ,  Michael Achter ,  Hagop Artin Nazarian

IPC分类号： G11C16/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/04

摘要： Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.

摘要翻译： 提出了使用确定性编程技术来促进存储器中的存储器元件的有效编程的系统，方法和设备。 存储器组件包括优化的程序组件，其可以部分地基于存储器元件的相应电流阈值电压电平（Vt）将被选择用于编程的一组存储器元件划分为期望数量的子组; 将相应的编程脉冲施加到各个子组中的每个存储元件; 在脉冲之后测量存储器元件的各个Vt电平; 并且验证为满足目标Vt的传递的存储器元件。优化的程序组件可以部分地基于存储器元件的相应的当前Vt级别将不满足目标Vt的存储器元件的子集划分为期望数量的子组，并且可以 继续执行此确定性编程过程，直到所有存储器元素被验证为传递目标Vt为止。

公开(公告)号：US20090103357A1

公开(公告)日：2009-04-23

申请号：US11874076

申请日：2007-10-17

申请人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

发明人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C2211/5621

摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.

摘要翻译： 提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。 交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。 在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。 选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。 学习元件对被编程以确定每个程序级的学习程序漏极电压。 这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

公开(公告)号：US07130210B2

公开(公告)日：2006-10-31

申请号：US11034642

申请日：2005-01-13

申请人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

发明人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

IPC分类号： G11C17/00

CPC分类号： G11C16/16 ,  G11C11/5671

摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

公开(公告)号：US20100142284A1

公开(公告)日：2010-06-10

申请号：US12330928

申请日：2008-12-09

申请人： Fatima Bathul ,  Darlene Gay Hamilton ,  Michael Achter ,  Hagop Artin Nazarian

发明人： Fatima Bathul ,  Darlene Gay Hamilton ,  Michael Achter ,  Hagop Artin Nazarian

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/04

摘要： Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.

摘要翻译： 提出了使用确定性编程技术来促进存储器中的存储器元件的有效编程的系统，方法和设备。 存储器组件包括优化的程序组件，其可以部分地基于存储器元件的相应电流阈值电压电平（Vt）将被选择用于编程的一组存储器元件划分为期望数量的子组; 将相应的编程脉冲施加到各个子组中的每个存储元件; 在脉冲之后测量存储元件的各个Vt电平; 并且验证为满足目标Vt的传递的存储器元件。优化的程序组件可以部分地基于存储器元件的相应的当前Vt级别将不满足目标Vt的存储器元件的子集划分为期望数量的子组，并且可以 继续执行此确定性编程过程，直到所有存储器元素被验证为传递目标Vt为止。