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    High-speed internal bus architecture for an integrated circuit
    1.
    发明申请
    High-speed internal bus architecture for an integrated circuit 有权
    用于集成电路的高速内部总线架构

    公开(公告)号：US20060282605A1

    公开(公告)日：2006-12-14

    申请号：US11149553

    申请日：2005-06-10

    申请人： David Avishai ,  Eliezer Weitz ,  Yehiel Engel ,  Raanan Gewirtzman

    发明人： David Avishai ,  Eliezer Weitz ,  Yehiel Engel ,  Raanan Gewirtzman

    IPC分类号： G06F13/36

    CPC分类号： G06F13/36 ,  G06F13/4059

    摘要： An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.

    摘要翻译： 内部总线架构，能够提供与集成电路（例如专用集成电路（ASIC））连接的模块之间的高速互连和互通。 内部总线架构包括用于与ASIC的模块进行接口的多个接口单元和耦合到接口单元的至少一个基本模块单元，用于允许在接口单元之间同时进行数据传输。 每个基本模块单元具有用于传送上游数据的上传单元和用于传送下游数据的下载单元。

    High-speed internal bus architecture for an integrated circuit
    2.
    发明授权
    High-speed internal bus architecture for an integrated circuit 有权
    用于集成电路的高速内部总线架构

    公开(公告)号：US07370127B2

    公开(公告)日：2008-05-06

    申请号：US11149553

    申请日：2005-06-10

    申请人： David Avishai ,  Eliezer Weitz ,  Yehiel Engel ,  Raanan Gewirtzman

    发明人： David Avishai ,  Eliezer Weitz ,  Yehiel Engel ,  Raanan Gewirtzman

    IPC分类号： G06F3/00

    CPC分类号： G06F13/36 ,  G06F13/4059

    摘要： An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.

    摘要翻译： 内部总线架构，能够提供与集成电路（例如专用集成电路（ASIC））连接的模块之间的高速互连和互通。 内部总线架构包括用于与ASIC的模块进行接口的多个接口单元和耦合到接口单元的至少一个基本模块单元，用于允许在接口单元之间同时进行数据传输。 每个基本模块单元具有用于传送上游数据的上传单元和用于传送下游数据的下载单元。