Frequency adapter utilized in high-speed internal buses
    1.
    发明授权
    Frequency adapter utilized in high-speed internal buses 有权
    频率适配器用于高速内部总线

    公开(公告)号:US08555104B2

    公开(公告)日:2013-10-08

    申请号:US12686714

    申请日:2010-01-13

    CPC分类号: G06F5/06 G06F1/12

    摘要: A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization unit is clocked by a low frequency clock.

    摘要翻译: 一种频率适配器,用于在低频模块和连接到内部总线的高频模块之间进行数据传输。 所述频率适配器包括用于同步从低频模块到高频模块的数据传输的低到高同步单元,其中所述低到高同步单元由低频时钟计时; 以及从高频模块到低频模块的数据传输同步的高到低的同步单元,其中由高频到低频的时钟来计时。

    High-speed internal bus architecture for an integrated circuit
    2.
    发明申请
    High-speed internal bus architecture for an integrated circuit 有权
    用于集成电路的高速内部总线架构

    公开(公告)号:US20060282605A1

    公开(公告)日:2006-12-14

    申请号:US11149553

    申请日:2005-06-10

    IPC分类号: G06F13/36

    CPC分类号: G06F13/36 G06F13/4059

    摘要: An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.

    摘要翻译: 内部总线架构,能够提供与集成电路(例如专用集成电路(ASIC))连接的模块之间的高速互连和互通。 内部总线架构包括用于与ASIC的模块进行接口的多个接口单元和耦合到接口单元的至少一个基本模块单元,用于允许在接口单元之间同时进行数据传输。 每个基本模块单元具有用于传送上游数据的上传单元和用于传送下游数据的下载单元。

    Adaptive forward error correction in passive optical networks
    3.
    发明授权
    Adaptive forward error correction in passive optical networks 有权
    无源光网络中的自适应前向纠错

    公开(公告)号:US09209897B2

    公开(公告)日:2015-12-08

    申请号:US13331255

    申请日:2011-12-20

    摘要: A method for an adaptive forward error correction (FEC) in a passive optical network. The method comprises selecting an initial downstream FEC code to be applied on downstream data transmitted from an optical line terminal (OLT) to a plurality of optical network units (ONUs) of the PON; communicating the selected downstream FEC code to the plurality of ONUs; receiving at least one downstream bit error ratio (BER) value from at least one ONU of the plurality of ONUs, wherein the downstream BER value is measured respective to downstream data received at the at least one ONU; changing the selected downstream FEC code to a new downstream FEC code based on a plurality of downstream BER values measured by the at least one ONU; and communicating the new downstream FEC code to the plurality of ONUs.

    摘要翻译: 一种无源光网络中自适应前向纠错(FEC)的方法。 该方法包括选择要应用于从光线路终端(OLT)发送到PON的多个光网络单元(ONU)的下行数据的初始下游FEC码; 将所选择的下游FEC码传送到所述多个ONU; 从所述多个ONU中的至少一个ONU接收至少一个下行误码率(BER)值,其中所述下行BER值被相应地测量在所述至少一个ONU处接收的下行数据; 基于由所述至少一个ONU测量的多个下游BER值,将所选择的下游FEC码改变为新的下行FEC码; 以及将所述新的下行FEC码传送到所述多个ONU。

    APPARATUS AND METHOD FOR PERFORMING LINE ANALYSIS OF CONTINUOUS DATA SIGNALS
    4.
    发明申请
    APPARATUS AND METHOD FOR PERFORMING LINE ANALYSIS OF CONTINUOUS DATA SIGNALS 有权
    连续数据信号线分析的装置和方法

    公开(公告)号:US20090274455A1

    公开(公告)日:2009-11-05

    申请号:US12434051

    申请日:2009-05-01

    IPC分类号: H04B10/08

    CPC分类号: H04B10/0795

    摘要: An apparatus for performing an optical line analysis of continuous data signals. The apparatus comprise a phase position processor for computing a phase early/late indicator; a phase control code processor for computing a difference phase indicator; a frequency extractor for computing a low frequency jitter indicator; and a statistical calculator for computing a plurality of statistical measures regarding frequency and amplitude components of a jitter of an input continuous data signal, wherein the statistical measures are computed based on one of the phase early/late information indicator, the difference phase indicator, or the low frequency jitter indicator.

    摘要翻译: 一种用于对连续数据信号进行光线分析的装置。 该装置包括用于计算相位早/晚指标的相位位置处理器; 用于计算差相位指示符的相位控制代码处理器; 用于计算低频抖动指示器的频率提取器; 以及统计计算器,用于计算关于输入连续数据信号的抖动的频率和幅度分量的多个统计测量,其中所述统计测量是基于所述相位早/晚信息指示符,所述差相位指示符或 低频抖动指示器。

    Burst mode clock and data recovery circuit and method
    5.
    发明申请
    Burst mode clock and data recovery circuit and method 失效
    突发模式时钟和数据恢复电路及方法

    公开(公告)号:US20080124092A1

    公开(公告)日:2008-05-29

    申请号:US11604748

    申请日:2006-11-28

    IPC分类号: H04L7/00 H04B10/00

    摘要: Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.

    摘要翻译: 突发模式时钟和数据恢复(BCDR)电路和方法,能够快速地对无源光网络(PON)业务进行数据恢复。 从输入突发数据信号产生过采样数据流,相位内插器使用参考时钟和相位信息产生采样时钟信号。 相位估计单元(PEU)确定过采样数据流中的相位误差; 并且相位检索单元在接收输入的突发数据信号之前,将相位内插器与输入的脉冲串数据信号的各自的相位信息相对应。

    Burst mode clock and data recovery circuit and method
    6.
    发明授权
    Burst mode clock and data recovery circuit and method 失效
    突发模式时钟和数据恢复电路及方法

    公开(公告)号:US08243869B2

    公开(公告)日:2012-08-14

    申请号:US11604748

    申请日:2006-11-28

    IPC分类号: H03D3/24

    摘要: Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.

    摘要翻译: 突发模式时钟和数据恢复(BCDR)电路和方法,能够快速地对无源光网络(PON)业务进行数据恢复。 从输入突发数据信号产生过采样数据流,相位内插器使用参考时钟和相位信息产生采样时钟信号。 相位估计单元(PEU)确定过采样数据流中的相位误差; 并且相位检索单元在接收输入的突发数据信号之前,将相位内插器与输入的脉冲串数据信号的各自的相位信息相对应。

    APPARATUS AND METHOD FOR PERFORMING LINE ANALYSIS OF CONTINUOUS DATA SIGNALS
    7.
    发明申请
    APPARATUS AND METHOD FOR PERFORMING LINE ANALYSIS OF CONTINUOUS DATA SIGNALS 有权
    连续数据信号线分析的装置和方法

    公开(公告)号:US20120093499A1

    公开(公告)日:2012-04-19

    申请号:US13306326

    申请日:2011-11-29

    IPC分类号: H04B17/00 H04B10/00

    CPC分类号: H04B10/0795

    摘要: A method for performing an optical line analysis of continuous data signals transmitted in a passive optical network (PON). The method comprises determining, from an optical signal of the optical line, at least one of a phase early/late indicator based on a phase position of an input continuous data signal relative to sampling clock signals, a difference phase indicator based on an input phase control code, and a low frequency jitter indicator based on an input phase control code; computing a plurality of statistical measures regarding frequency and amplitude components of a jitter of the input continuous data signal, wherein the statistical measures are computed based on one of the phase early/late information indicator, the difference phase indicator, and the low frequency jitter indicator; and analyzing the plurality of statistical measures to detect optical failures in the PON and determining a root cause of each of the detected failures.

    摘要翻译: 一种用于对在无源光网络(PON)中发送的连续数据信号执行光线分析的方法。 该方法包括:从光线路的光信号,基于相对于采样时钟信号的输入连续数据信号的相位位置来确定相位早/晚指示符中的至少一个,基于输入相位的差相位指示符 控制代码和基于输入相位控制代码的低频抖动指示器; 计算关于输入连续数据信号的抖动的频率和幅度分量的多个统计量度,其中基于相位早/晚信息指示符,差相位指示符和低频抖动指示器之一来计算统计测量值 ; 并且分析多个统计测量以检测PON中的光学故障并确定每个检测到的故障的根本原因。

    Apparatus and method for performing line analysis of continuous data signals
    8.
    发明授权
    Apparatus and method for performing line analysis of continuous data signals 有权
    对连续数据信号执行线分析的装置和方法

    公开(公告)号:US08111985B2

    公开(公告)日:2012-02-07

    申请号:US12434051

    申请日:2009-05-01

    IPC分类号: H04B10/08 H04B10/00

    CPC分类号: H04B10/0795

    摘要: An apparatus for performing an optical line analysis of continuous data signals. The apparatus comprise a phase position processor for computing a phase early/late indicator; a phase control code processor for computing a difference phase indicator; a frequency extractor for computing a low frequency jitter indicator; and a statistical calculator for computing a plurality of statistical measures regarding frequency and amplitude components of a jitter of an input continuous data signal, wherein the statistical measures are computed based on one of the phase early/late information indicator, the difference phase indicator, or the low frequency jitter indicator.

    摘要翻译: 一种用于对连续数据信号进行光线分析的装置。 该装置包括用于计算相位早/晚指标的相位位置处理器; 用于计算差相位指示符的相位控制代码处理器; 用于计算低频抖动指示器的频率提取器; 以及统计计算器,用于计算关于输入连续数据信号的抖动的频率和幅度分量的多个统计测量,其中所述统计测量是基于所述相位早/晚信息指示符,所述差相位指示符或 低频抖动指示器。

    FREQUENCY ADAPTER UTILIZED IN HIGH-SPEED INTERNAL BUSES
    9.
    发明申请
    FREQUENCY ADAPTER UTILIZED IN HIGH-SPEED INTERNAL BUSES 有权
    频率适配器应用于高速内部总线

    公开(公告)号:US20110173481A1

    公开(公告)日:2011-07-14

    申请号:US12686714

    申请日:2010-01-13

    IPC分类号: G06F1/04 G06F13/42

    CPC分类号: G06F5/06 G06F1/12

    摘要: A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization module is clocked by a low frequency clock.

    摘要翻译: 一种频率适配器,用于在低频模块和连接到内部总线的高频模块之间进行数据传输。 所述频率适配器包括用于同步从低频模块到高频模块的数据传输的低到高同步单元,其中所述低到高同步单元由低频时钟计时; 以及用于同步从高频模块到低频模块的数据传输的高到低的同步单元,其中,从低到低的同步模块由低频时钟计时。