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公开(公告)号：US20090172361A1
公开(公告)日：2009-07-02
申请号：US11967430
申请日：2007-12-31
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
摘要翻译： 公开了一种用于微处理器的线程切换机制和技术，其中完成了第一线程的处理，并且在完成第一线程期间开始了第二线程的延续。 在一种形式中，该技术包括处理处理设备的流水线处的第一线程，以及响应于上下文切换事件的发生，在流水线的前端开始处理第二线程。 该技术还可以包括响应于上下文切换事件发起指令进展度量。 该技术还可以包括在上下文切换事件发生时能够完成在流水线的后端处理第一线程的指令，直到指令进度度量的到期为止。
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2.发明授权Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor 有权基于微处理器的指令进度指标机制，完成线程切换公开(公告)号：US07941646B2
公开(公告)日：2011-05-10
申请号：US11967430
申请日：2007-12-31
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
摘要翻译： 公开了一种用于微处理器的线程切换机制和技术，其中完成了第一线程的处理，并且在完成第一线程期间开始了第二线程的延续。 在一种形式中，该技术包括处理处理设备的流水线处的第一线程，以及响应于上下文切换事件的发生，在流水线的前端开始处理第二线程。 该技术还可以包括响应于上下文切换事件发起指令进展度量。 该技术还可以包括在上下文切换事件发生时能够完成在流水线的后端处理第一线程的指令，直到指令进度度量的到期为止。
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公开(公告)号：US20080209182A1
公开(公告)日：2008-08-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F9/302
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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公开(公告)号：US08117618B2
公开(公告)日：2012-02-14
申请号：US11871626
申请日：2007-10-12
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.
摘要翻译： 处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。 处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。 处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。 所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。
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5.发明授权Multiple address and arithmetic bit-mode data processing device and methods thereof 有权多地址和算术位模式数据处理装置及其方法公开(公告)号：US07805581B2
公开(公告)日：2010-09-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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公开(公告)号：US20090100432A1
公开(公告)日：2009-04-16
申请号：US11871626
申请日：2007-10-12
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.
摘要翻译： 处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。 处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。 处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。 所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。
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7.发明授权Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation 有权调试指令由第一个线程执行以在第二个线程中生成调试事件以导致暂停操作公开(公告)号：US09395983B2
公开(公告)日：2016-07-19
申请号：US12195220
申请日：2008-08-20
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译： 为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。 该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。
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公开(公告)号：US08531899B2
公开(公告)日：2013-09-10
申请号：US13613630
申请日：2012-09-13
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译： 存储器系统具有包括冗余列的存储器单元阵列的第一存储器。 冗余列代替数组中的第一列。 第一列包括测试存储单元。 阵列接收电源电压。 测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。 存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。 这对于对应用于阵列的电源电压的值做出决定是有用的。
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9.发明授权Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand 有权用于确定第一操作数和第二操作数的逻辑和是否与第三操作数相同的技术公开(公告)号：US08380779B2
公开(公告)日：2013-02-19
申请号：US12474451
申请日：2009-05-29
IPC分类号： G06F7/50
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译： 系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。 这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。 例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。 通过参考以下描述和附图可以更好地理解这一点。
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10.发明授权Integrated circuit having an embedded memory and method for testing the memory 有权具有嵌入式存储器的集成电路和用于测试存储器的方法公开(公告)号：US08379466B2
公开(公告)日：2013-02-19
申请号：US12414758
申请日：2009-03-31
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译： 存储器系统具有包括冗余列的存储器单元阵列的第一存储器。 冗余列替代数组中的第一列。 第一列包括测试存储单元。 阵列接收电源电压。 测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。 存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。 这对于对应用于阵列的电源电压的值做出决定是有用的。
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