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1.发明授权Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand 有权用于确定第一操作数和第二操作数的逻辑和是否与第三操作数相同的技术公开(公告)号：US08380779B2
公开(公告)日：2013-02-19
申请号：US12474451
申请日：2009-05-29
IPC分类号： G06F7/50
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译： 系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。 这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。 例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。 通过参考以下描述和附图可以更好地理解这一点。
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2.发明申请TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND 有权如果第一个操作的逻辑关系和第二个操作与第三个操作相同，则用于确定的技术公开(公告)号：US20100306302A1
公开(公告)日：2010-12-02
申请号：US12474451
申请日：2009-05-29
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译： 系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。 这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。 例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。 通过参考以下描述和附图可以更好地理解这一点。
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公开(公告)号：US20110194325A1
公开(公告)日：2011-08-11
申请号：US12703528
申请日：2010-02-10
CPC分类号： G11C15/04 , G06F11/1064 , G11C29/52
摘要： A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.
摘要翻译： 内容可寻址存储器和操作方法使用具有多行存储的内容可寻址存储器数据的存储器阵列和用于将接收到的比较数据与存储的内容可寻址存储器数据进行比较的比较电路。 为每行提供命中信号和一个或多个奇偶校验位。 耦合到每行的存储器阵列的错误的命中检测电路响应于比较数据的奇偶性与与命中信号相关联的行的奇偶校验之间的比较，产生行错误指示，如通过断言该命中信号的命中信号 行。 错误的命中检测电路使用每一行的行错误指示符来提供指示至少一个被断言的命中信号是否对应于错误命中的输出。
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公开(公告)号：US08199547B2
公开(公告)日：2012-06-12
申请号：US12703528
申请日：2010-02-10
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G06F11/1064 , G11C29/52
摘要： A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.
摘要翻译： 内容可寻址存储器和操作方法使用具有多行存储的内容可寻址存储器数据的存储器阵列和用于将接收到的比较数据与存储的内容可寻址存储器数据进行比较的比较电路。 为每行提供命中信号和一个或多个奇偶校验位。 耦合到每行的存储器阵列的错误的命中检测电路响应于比较数据的奇偶性与与命中信号相关联的行的奇偶校验之间的比较，产生行错误指示，如通过断言该命中信号的命中信号 行。 错误的命中检测电路使用每一行的行错误指示符来提供指示至少一个被断言的命中信号是否对应于错误命中的输出。
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5.发明授权Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors 有权跟踪和关联无序处理器的数据跟踪和指令跟踪的方法和装置公开(公告)号：US08122437B2
公开(公告)日：2012-02-21
申请号：US12058874
申请日：2008-03-31
申请人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
发明人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
CPC分类号： G06F11/3636
摘要： In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.
摘要翻译： 在数据处理系统中，使用标记位来标识整个流水线中的数据访问指令，以指示该指令满足用户指定的标准（例如，满足感兴趣的数据地址范围）。 基于标记位，产生一个顺序程序相关消息，指示何时相对于指令流发生数据访问指令。 标记位还用于生成按顺序数据跟踪消息。 因此，仅包括满足用户指定标准的数据访问指令的跟踪流可以被后处理并且精确地相关联。
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公开(公告)号：US07827360B2
公开(公告)日：2010-11-02
申请号：US11832797
申请日：2007-08-02
申请人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0891
摘要： A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
摘要翻译： 公开了一种用于锁定高速缓存的高速缓存行的方法和设备。 该方法包括响应于接收到高速缓存行外部的对应于高速缓存行的存储器位置与处理器的访问请求相关联的指示，自动将高速缓存行的状态从有效锁定状态改变为无效锁定状态 或其他数据访问模块。 因此，即使在锁定的高速缓存行中的数据无效之后，也保持高速缓存行的锁定状态。 通过保持无效的锁定状态，高速缓存行不可用于高速缓存的重新分配。 这允许被锁定的高速缓存行保持锁定，而不需要额外的软件开销来定期确定锁是否由于高速缓存行的无效而丢失。
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公开(公告)号：US08832702B2
公开(公告)日：2014-09-09
申请号：US11746998
申请日：2007-05-10
CPC分类号： G06F9/485 , G06F9/3009 , G06F9/3013 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
摘要翻译： 公开了一种用于在处理器处调度线程执行的技术。 该技术包括执行线程的线程去加重指令，其不强调线程，直到与该线程相关联的等待存储器事务（例如高速缓存未命中）的数量处于或低于阈值。 当该线程被去加强时，处理器中具有较高优先级的其他线程可以执行或分配系统资源。 因此，处理器中失速的可能性降低。
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8.发明申请Method and Apparatus to Trace and Correlate Data Trace and Instruction Trace for Out-of-Order Processors 有权跟踪和关联无序处理器的数据跟踪和指令跟踪的方法和设备公开(公告)号：US20090249302A1
公开(公告)日：2009-10-01
申请号：US12058874
申请日：2008-03-31
申请人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
发明人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
IPC分类号： G06F9/44
CPC分类号： G06F11/3636
摘要： In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.
摘要翻译： 在数据处理系统中，使用标记位来标识整个流水线中的数据访问指令，以指示该指令满足用户指定的标准（例如，满足感兴趣的数据地址范围）。 基于标记位，产生一个顺序程序相关消息，指示何时相对于指令流发生数据访问指令。 标记位还用于生成按顺序数据跟踪消息。 因此，仅包括满足用户指定标准的数据访问指令的跟踪流可以被后处理并且精确地相关联。
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9.发明申请SYSTEM AND METHOD FOR PROCESSING POTENTIALLY SELF-INCONSISTENT MEMORY TRANSACTIONS 有权用于处理潜在的自发存储器交易的系统和方法公开(公告)号：US20090164737A1
公开(公告)日：2009-06-25
申请号：US11962331
申请日：2007-12-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F12/0831 , G06F2212/1016 , G06F2212/507
摘要： A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.
摘要翻译： 处理器为与存储器请求相关联的一致性粒子提供存储器请求和一致性状态值。 处理器还根据一致性状态值是否表示处理器的多个高速缓存的累积一致性状态来进一步提供第一指示符或第二指示符。 第一指示符和第二指示符分别表示相关性状态值，表示累积相关性状态或潜在的非累积一致性状态。 如果提供了第二指示符，则事务管理模块响应于接收到第二指示符来确定是否请求相关性颗粒的累积一致性状态。 响应于确定请求累积一致性状态，事务管理模块向处理器提供对累积一致性状态的请求的指示符。 否则，事务管理模块处理存储器事务而不请求累积一致性状态。
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公开(公告)号：US20090113137A1
公开(公告)日：2009-04-30
申请号：US11929180
申请日：2007-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/122
摘要： A multi-way cache system includes multi-way cache storage circuitry, a pseudo least recently used (PLRU) tree state representative of a PLRU tree, the PLRU tree having a plurality of levels, and PLRU control circuitry coupled to the multi-way cache storage circuitry and the PLRU tree state. The PLRU control circuitry has programmable PLRU tree level update enable circuitry which selects Y levels of the plurality of levels of the PLRU tree to be updated. The PLRU control circuitry, in response to an address hitting or resulting in an allocation in the multi-way cache storage circuitry, updates only the selected Y levels of the PLRU tree state.
摘要翻译： 多路缓存系统包括多路缓存存储电路，代表PLRU树的伪最近最少使用（PLRU）树状态，具有多个电平的PLRU树，以及耦合到多路缓存的PLRU控制电路 存储电路和PLRU树状态。 PLRU控制电路具有可编程PLRU树级更新使能电路，其选择要更新的PLRU树的多个级别的Y级。 PLRU控制电路响应于在多路高速缓存存储电路中的分配地址或导致分配，仅更新PLRU树状态的所选Y级。
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