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1.发明申请IO DRIVER CIRCUIT WITH OUTPUT STAGE CONFIGURABLE AS A THEVENIN TERMINATOR 审中-公开具有可配置为输出端的输出驱动电路作为电源终端公开(公告)号：US20090153216A1
公开(公告)日：2009-06-18
申请号：US11955023
申请日：2007-12-12
IPC分类号： H03L5/00
CPC分类号： H03K19/0005 , H03K19/018592 , H04L25/0278
摘要： An IO driver circuit incorporates an output stage control circuit that selectively configures an output stage for the IO driver circuit to operate as a thevenin termination whenever the IO driver circuit is receiving a signal from an input/output node to which the IO driver circuit is coupled. The output stage may include a plurality of branches, with each branch having a pull-up device and a pull-down device, and the output stage control circuit selectively activates the pull-up devices in a first subset of branches in the output stage while concurrently activating the pull-down devices in a second subset of branches, as well as while leaving the pull-up devices in the second subset of branches and the pull-down devices in the first subset of branches deactivated.
摘要翻译： IO驱动器电路包括输出级控制电路，其选择性地配置用于IO驱动器电路的输出级，以便当IO驱动器电路从IO驱动器电路耦合到的输入/输出节点接收信号时作为终端终止 。 输出级可以包括多个分支，每个分支具有上拉装置和下拉装置，并且输出级控制电路选择性地激活输出级中的第一分支子集中的上拉装置，同时 同时激活分支的第二子集中的下拉装置，以及在分支的第二子集中的上拉装置和第一分支子集中的下拉装置停用时。
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公开(公告)号：US07102389B2
公开(公告)日：2006-09-05
申请号：US10926934
申请日：2004-08-26
IPC分类号： H03K19/0175
CPC分类号： H03K3/356165 , H03K3/356104 , H03K3/356113 , H03K17/08122 , H03K19/00384 , H03K19/018521
摘要： A voltage translator with data buffer includes an input inverter receiving a data input signal at a first voltage level. A level shifting cross-coupled NOR circuit is coupled to the input inverter for translating the data input signal at a second voltage level. An output stage driven by the level shifting cross-coupled NOR circuit for providing a data output signal at the second voltage level. The voltage translator enables improved performance across various power, voltage and temperature (PVT) conditions and reliably reduces or minimizes shoot through current and delay.
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公开(公告)号：US20090267641A1
公开(公告)日：2009-10-29
申请号：US12258704
申请日：2008-10-27
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.
摘要翻译： I / O驱动器具有v / i特性控制，用于使用I / O输出板上的传输门配置来维持基本平坦的输出阻抗响应。 该配置包括在I / O焊盘处电连接以限制经处理的数据I / O信号的线性电阻元件，用于接收和处理数据信号的有源阻抗元件，其包括由一系列电压状态转换表示的数据，以及 上拉和下拉阵列校准字，用于在切换数据信号时产生并输出经过处理的I / O输出信号到电阻元件以输出基本平坦的v / i响应。
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公开(公告)号：US07501875B1
公开(公告)日：2009-03-10
申请号：US11863633
申请日：2007-09-28
IPC分类号： H03L5/00
CPC分类号： H03K3/35613
摘要： A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.
摘要翻译： 用于高速差分电压电平移位器电路装置的设计利用由输入控制的PFET和NFET来确定输出的状态，这最小化或消除了在从一个状态切换到另一个状态时对内部节点的争用。 因此，该设计可最大限度地减少不匹配的NFET和PFET器件强度的不利影响，并且便于在高频下的使用以及电平转换到输出电压电平的范围。 该设计还适用于电平转换到更高或更低输出电压。
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公开(公告)号：US07443194B1
公开(公告)日：2008-10-28
申请号：US12109285
申请日：2008-04-24
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.
摘要翻译： I / O驱动器具有v / i特性控制，用于使用I / O输出板上的传输门配置来维持基本平坦的输出阻抗响应。 该配置包括在I / O焊盘处电连接以限制经处理的数据I / O信号的线性电阻元件，用于接收和处理数据信号的有源阻抗元件，其包括由一系列电压状态转换表示的数据，以及 上拉和下拉阵列校准字，用于在切换数据信号时产生并输出经过处理的I / O输出信号到电阻元件以输出基本平坦的v / i响应。
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公开(公告)号：US08149014B2
公开(公告)日：2012-04-03
申请号：US12258704
申请日：2008-10-27
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.
摘要翻译： I / O驱动器具有v / i特性控制，用于使用I / O输出板上的传输门配置来维持基本平坦的输出阻抗响应。 该配置包括在I / O焊盘处电连接以限制经处理的数据I / O信号的线性电阻元件，用于接收和处理数据信号的有源阻抗元件，其包括由一系列电压状态转换表示的数据，以及 上拉和下拉阵列校准字，用于在切换数据信号时产生并输出经过处理的I / O输出信号到电阻元件以输出基本平坦的v / i响应。
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公开(公告)号：US20090085635A1
公开(公告)日：2009-04-02
申请号：US11863633
申请日：2007-09-28
IPC分类号： H03L5/00
CPC分类号： H03K3/35613
摘要： A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.
摘要翻译： 用于高速差分电压电平移位器电路装置的设计利用由输入控制的PFET和NFET来确定输出的状态，这最小化或消除了在从一个状态切换到另一个状态时对内部节点的争用。 因此，该设计可最大限度地减少不匹配的NFET和PFET器件强度的不利影响，并且便于在高频下的使用以及电平转换到输出电压电平的范围。 该设计还适用于电平转换到更高或更低输出电压。
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公开(公告)号：US20080191745A1
公开(公告)日：2008-08-14
申请号：US12106698
申请日：2008-04-21
IPC分类号： H03K19/094 , H03K3/00
CPC分类号： H03K19/01855 , G11C7/1078 , G11C7/1084 , H03K3/356113 , H03K19/0948
摘要： A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.
摘要翻译： 在高电压域和低电压域之间使用高速差分接收器。 高速差分接收机包括耦合到差分电平转换器的共模差分放大器。 共模差分放大器和差分电平转换器在高电压域工作。 差分电平移位器从共模差分放大器接收放大的差分信号，并提供施加到在低电压域工作的偏置差分放大器的电压电平移位差分信号。
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公开(公告)号：US07385424B2
公开(公告)日：2008-06-10
申请号：US11171723
申请日：2005-06-30
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/01855 , G11C7/1078 , G11C7/1084 , H03K3/356113 , H03K19/0948
摘要： A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.
摘要翻译： 在高电压域和低电压域之间使用高速差分接收器。 高速差分接收机包括耦合到差分电平转换器的共模差分放大器。 共模差分放大器和差分电平转换器在高电压域工作。 差分电平移位器从共模差分放大器接收放大的差分信号，并提供施加到在低电压域工作的偏置差分放大器的电压电平移位的差分信号。
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10.发明授权CMOS tri-state control circuit for a bidirectional I/O with slew rate control 有权CMOS三态控制电路，用于具有压摆率控制的双向I / O
公开(公告)号：US6163169A
公开(公告)日：2000-12-19
申请号：US132803
申请日：1998-08-13
IPC分类号： H03K17/16 , H03K19/003 , H03K19/094 , H03K19/00
CPC分类号： H03K19/00361 , H03K17/164 , H03K19/09429
摘要： A digital circuit pulls up an output node using an NFET device. The digital circuit is part of a CMOS predriver having balanced delays for coming out of tristate mode and for data mode operation. The predriver has size and speed capability advantages and is particularly advantageous when followed by a CMOS driver powered by a lower positive voltage supply.
摘要翻译： 数字电路使用NFET器件拉出输出节点。 数字电路是CMOS预驱动器的一部分，具有从三态模式和数据模式操作出来的平衡延迟。 预驱动器具有尺寸和速度能力的优点，并且在由较低的正电压源供电的CMOS驱动器之后是特别有利的。
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