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公开(公告)号：US5661395A
公开(公告)日：1997-08-26
申请号：US534900
申请日：1995-09-28
CPC分类号： G05F3/242
摘要： A current source circuit that operates advantageously in the linear region of an FET and that minimizes any voltage drop at its output node which is not load related. The circuit operates under the principle that the output current is dynamically measured without introducing any elements that affects the voltage drop across the FET. Its current source includes a pass device with feedback control, such that a constant current is obtained regardless of the load placed at the output terminal. The operation of the pass device is mirrored by a second pass device having physical dimension that only a fraction of those of the first pass device. A high input impedance differential amplifier, driven by the respective outputs of the first and second pass devices, forces the mirror pass device to the identical voltage as the first pass device.
摘要翻译： 一种电流源电路，其有利地在FET的线性区域中工作，并且使其输出节点处的任何电压降最小化，其不负载相关。 该电路的工作原理是输出电流被动态测量而不引入任何影响FET两端的电压降的元件。 其电流源包括具有反馈控制的通过装置，使得获得恒定电流，而不管放置在输出端子处的负载如何。 通过装置的操作由具有物理尺寸的第二通过装置镜像，该尺寸仅为第一通过装置的一部分。 由第一和第二通过装置的相应输出驱动的高输入阻抗差分放大器迫使镜面传递装置与第一通过装置相同的电压。
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公开(公告)号：US5805088A
公开(公告)日：1998-09-08
申请号：US740811
申请日：1996-11-01
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers. A third clock triggers the fifth and sixth registers simultaneously to latch bits 0 and 2, respectively, of a series of four bits. A fourth clock triggers the seventh and eight registers simultaneously to latch bits 1 and 3, respectively, of the series of four bits.
摘要翻译： 设备将基于一个时钟的串行数据转换为基于不同异步时钟的并行数据。 数据转换器包括一个包括第一和第二寄存器的寄存器组和包括第三和第四寄存器的另一寄存器组。 第一寄存器的数据输入和第三寄存器的数据输入被耦合以接收串行数据。 第二寄存器的数据输入耦合到第一寄存器的数据输出。 第四寄存器的数据输入耦合到第三寄存器的数据输出。 第一时钟同时触发第一和第二寄存器，第二时钟同时触发第三和第四寄存器。 第一和第二时钟彼此交替。 第五，第六，第七和第八寄存器具有耦合到第一，第二，第三和第四寄存器的相应数据输出的各自的数据输入。 第三个时钟同时触发第五和第六寄存器，分别锁存一系列四位的位0和2。 第四个时钟同时触发第七个和第八个寄存器，分别锁存四个比特序列中的位1和3。
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公开(公告)号：US08130887B2
公开(公告)日：2012-03-06
申请号：US12124106
申请日：2008-05-20
申请人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
发明人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L2207/50
摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。
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公开(公告)号：US20080285695A1
公开(公告)日：2008-11-20
申请号：US12124106
申请日：2008-05-20
申请人： Hayden Clavie Cranford, JR. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
发明人： Hayden Clavie Cranford, JR. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L2207/50
摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。
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公开(公告)号：US07397876B2
公开(公告)日：2008-07-08
申请号：US10915790
申请日：2004-08-11
申请人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
发明人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
CPC分类号： H04L7/0337 , H03L7/091 , H03L2207/50
摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。
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