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    Programmable hash-tuple generation with parallel rule implementation independence
    1.
    发明授权
    Programmable hash-tuple generation with parallel rule implementation independence 有权
    可编程散列元组生成，并行规则实现独立

    公开(公告)号：US07894440B2

    公开(公告)日：2011-02-22

    申请号：US12404140

    申请日：2009-03-13

    Applicant: Kun Xu ,  David Kramer

    Inventor： Kun Xu ,  David Kramer

    IPC: H04L12/56

    CPC classification number: H04L45/00 ,  H04L45/745

    Abstract: Techniques have been developed to facilitate concurrent evaluation of hash rule entries in ways that allow an implementation to maintain a deterministic resultant hash irrespective of variations in the allocation of particular rules to particular storage banks or evaluation logic, such as may occur with rule set revisions. Similarly, uniform deterministic hash results can be assured even across a range of implementations that support greater or lesser levels of concurrent rule evaluations.

    Abstract translation: 已经开发了技术来促进哈希规则条目的并发评估，其方式允许实现维持确定性的合成散列，而不管特定规则对特定存储库或评估逻辑的分配的变化，例如可能随规则集修订而发生。 类似地，即使在支持更多或更少级别的并发规则评估的一系列实现中，也可以确保统一的确定性散列结果。

    PROGRAMMABLE HASH-TUPLE GENERATION WITH PARALLEL RULE IMPLEMENTATION INDEPENDENCE
    2.
    发明申请
    PROGRAMMABLE HASH-TUPLE GENERATION WITH PARALLEL RULE IMPLEMENTATION INDEPENDENCE 有权
    可编程HASH-TUPLE生成与并行规则实现独立性

    公开(公告)号：US20100232434A1

    公开(公告)日：2010-09-16

    申请号：US12404140

    申请日：2009-03-13

    Applicant: Kun Xu ,  David Kramer

    Inventor： Kun Xu ,  David Kramer

    IPC: H04L12/56

    CPC classification number: H04L45/00 ,  H04L45/745

    Abstract: Techniques have been developed to facilitate concurrent evaluation of hash rule entries in ways that allow an implementation to maintain a deterministic resultant hash irrespective of variations in the allocation of particular rules to particular storage banks or evaluation logic, such as may occur with rule set revisions. Similarly, uniform deterministic hash results can be assured even across a range of implementations that support greater or lesser levels of concurrent rule evaluations.

    Abstract translation: 已经开发了技术来促进哈希规则条目的并发评估，其方式允许实现维持确定性的合成散列，而不管特定规则对特定存储库或评估逻辑的分配的变化，例如可能随规则集修订而发生。 类似地，即使在支持更多或更少级别的并发规则评估的一系列实现中，也可以确保统一的确定性散列结果。

    Technique for generating hash-tuple independent of precedence order of applied rules
    3.
    发明授权
    Technique for generating hash-tuple independent of precedence order of applied rules 有权
    用于生成独立于应用规则的优先顺序的散列元组的技术

    公开(公告)号：US08638800B2

    公开(公告)日：2014-01-28

    申请号：US12418259

    申请日：2009-04-03

    Applicant: David Kramer ,  Kun Xu

    Inventor： David Kramer ,  Kun Xu

    IPC: H04L12/28

    CPC classification number: H04L45/745 ,  H04L69/22

    Abstract: Techniques have been developed to facilitate evaluation of match and hash rule entries in ways that allow an implementation to decouple (i) the order in which match rules are applied to a first subset of packet header fields from (ii) the ordering of a second subset of packet header fields over which a non-commutative hash is computed. In short, the set and ordering of fields evaluated in accordance with a precedence order of rules need not correspond to the set or ordering of fields over which a hash is computed in a communications controller.

    Abstract translation: 已经开发了技术来促进对匹配和散列规则条目的评估，以允许实现将匹配规则应用于分组报头字段的第一子集的顺序从（ii）第二子集的排序 的分组报头字段，在其上计算非可交换散列。 简而言之，根据规则的优先顺序来评估的字段的集合和排序不必对应于在通信控制器中计算散列的字段的集合或排序。

    TECHNIQUE FOR GENERATING HASH-TUPLE INDEPENDENT OF PRECEDENCE ORDER OF APPLIED RULES
    4.
    发明申请
    TECHNIQUE FOR GENERATING HASH-TUPLE INDEPENDENT OF PRECEDENCE ORDER OF APPLIED RULES 有权
    生成适用规则的先期顺序的产生技术

    公开(公告)号：US20100254391A1

    公开(公告)日：2010-10-07

    申请号：US12418259

    申请日：2009-04-03

    Applicant: David Kramer ,  Kun Xu

    Inventor： David Kramer ,  Kun Xu

    IPC: H04L12/56

    CPC classification number: H04L45/745 ,  H04L69/22

    Abstract: Techniques have been developed to facilitate evaluation of match and hash rule entries in ways that allow an implementation to decouple (i) the order in which match rules are applied to a first subset of packet header fields from (ii) the ordering of a second subset of packet header fields over which a non-commutative hash is computed. In short, the set and ordering of fields evaluated in accordance with a precedence order of rules need not correspond to the set or ordering of fields over which a hash is computed in a communications controller.

    Abstract translation: 已经开发了技术来促进对匹配和散列规则条目的评估，以允许实现将匹配规则应用于分组报头字段的第一子集的顺序从（ii）第二子集的排序 的分组报头字段，在其上计算非可交换散列。 简而言之，根据规则的优先顺序来评估的字段的集合和排序不必对应于在通信控制器中计算散列的字段的集合或排序。

    Systems and methods for direct memory access coherency among multiple processing cores
    7.
    发明授权
    Systems and methods for direct memory access coherency among multiple processing cores 有权
    在多个处理核心之间直接存储器访问一致性的系统和方法

    公开(公告)号：US09542238B2

    公开(公告)日：2017-01-10

    申请号：US13900761

    申请日：2013-05-23

    Applicant: Kun Xu ,  Tommi M. Jokinen ,  Zheng Xu

    Inventor： Kun Xu ,  Tommi M. Jokinen ,  Zheng Xu

    IPC: G06F9/46 ,  G06F9/52 ,  G06F9/48 ,  G06F9/50

    CPC classification number: G06F9/526 ,  G06F9/46 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5016 ,  G06F9/52

    Abstract: A multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine capable of selecting, by a task scheduler of a first core, a first task for execution by the first core. In response to a semaphore lock request, the task scheduler of the first core switches the first task to an inactive state and selects a next task for execution by the first core. After the semaphore engine acquires the semaphore lock of the first semaphore, a data transfer request is provided to the DMA engine. In response to the data transfer request, the DMA engine transfers data associated with the locked first semaphore to the entry of the workspace of the first core.

    Abstract translation: 一种多核系统，被配置为执行多个任务并具有能够由第一核心的任务调度器选择由第一核执行的第一任务的信号引擎和直接存储器访问（DMA）引擎。 响应于信号量锁定请求，第一核心的任务调度器将第一任务切换到非活动状态，并选择下一任务以由第一核执行。 在信号引擎获取第一信号量的信号锁之后，向DMA引擎提供数据传输请求。 响应于数据传输请求，DMA引擎将与锁定的第一信号量相关联的数据传送到第一核心的工作空间的入口。

    SYSTEM AND METHOD FOR CONDITIONAL TASK SWITCHING DURING ORDERING SCOPE TRANSITIONS
    8.
    发明申请
    SYSTEM AND METHOD FOR CONDITIONAL TASK SWITCHING DURING ORDERING SCOPE TRANSITIONS 有权
    系统和方法在订单范围转换期间进行条件性任务切换

    公开(公告)号：US20150355938A1

    公开(公告)日：2015-12-10

    申请号：US14300762

    申请日：2014-06-10

    Applicant: Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

    Inventor： Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

    IPC: G06F9/48

    CPC classification number: G06F9/4881 ,  G06F2209/484

    Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

    Abstract translation: 数据处理系统包括处理器核心和硬件模块。 处理器内核在数据包上执行任务。 订购范围管理器将第一个值存储在第一个存储位置。 第一个值表示启用第一个排序范围中的第一个任务的独占执行。 响应于接收到的放弃指示符，订购范围管理器将第二值存储在第一存储位置中。 第二个值表示第一个排序范围中的第一个任务的排他性执行被禁用。

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