公开(公告)号：US20050228952A1

公开(公告)日：2005-10-13

申请号：US10823300

申请日：2004-04-13

申请人： David Mayhew ,  Karl Meier ,  Todd Comins

发明人： David Mayhew ,  Karl Meier ,  Todd Comins

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0817

摘要： The present invention minimizes the amount of traffic that traverses the fabric in support of the cache coherency protocol. It also allows rapid transmission of all traffic associated with the cache coherency protocol, so as to minimize latency and maximize performance. A fabric is used to interconnect a number of processing units together. The switches are able to recognize incoming traffic related to the cache coherency protocol and then move these messages to the head of that switch's output queue to insure fast transmission. Also, the traffic related to the cache coherency protocol can interrupt an outgoing message, further reducing latency. The switch incorporates a memory element, dedicated to the cache coherency protocol, which tracks the contents of all of the caches of all of the processors connected to the fabric. In this way, the fabric can selectively transmit traffic only to the processors where it is relevant.

摘要翻译： 本发明最大限度地减少了支持高速缓存一致性协议的通过结构的业务量。 它还允许与高速缓存一致性协议相关联的所有业务的快速传输，以便最小化等待时间并最大化性能。 织物用于将多个处理单元互连在一起。 交换机能够识别与缓存一致性协议相关的传入流量，然后将这些消息移动到该交换机的输出队列的头部以确保快速传输。 此外，与缓存一致性协议相关的流量可以中断外发消息，进一步减少延迟。 该交换机包含专用于高速缓存一致性协议的存储器元件，其跟踪连接到该结构的所有处理器的所有高速缓存的内容。 以这种方式，结构可以选择性地将流量传输到与其相关的处理器。

公开(公告)号：US20050041658A1

公开(公告)日：2005-02-24

申请号：US10746043

申请日：2003-12-23

申请人： David Mayhew ,  Todd Comins ,  Lynne Brocco ,  Joseph Schaefer ,  Gary Solomon ,  Edward Butler

发明人： David Mayhew ,  Todd Comins ,  Lynne Brocco ,  Joseph Schaefer ,  Gary Solomon ,  Edward Butler

IPC分类号： H04L12/56

CPC分类号： H04L41/0803 ,  H04L49/65

摘要： A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.

摘要翻译： 描述用于访问设备的配置空间的方法。 该方法包括将分组的第一字段设置为指定目的设备的值，并将该分组的第二字段设置为定义的值，以指示该分组是配置接入分组。 该方法还包括将配置接入分组的第三字段设置为选择目的设备的配置空间的多个配置孔径中的一个，并将配置接入分组的第四个字段设置为寻址一个值 所选光圈内的特定存储器位置。

公开(公告)号：US07653060B2

公开(公告)日：2010-01-26

申请号：US11235346

申请日：2005-09-26

申请人： David Mayhew ,  Todd Comins

发明人： David Mayhew ,  Todd Comins

IPC分类号： H04L1/00

CPC分类号： H04L47/10 ,  H04L1/1838 ,  H04L1/1877 ,  H04L47/2416 ,  H04L47/26

摘要： The present invention provides a system and method for utilizing the Advanced Switching network protocol to communicate over long distances, such as multiple kilometers. The present invention utilizes an existing status bit, referred to as the Perishable Bit, within the AS packet header, to reduce the number of packets which must be stored in the retry buffer. This reduces the required size of the retry buffer and simultaneously reduces the latency associated with retransmitting time critical packets after NAKs are received. The receiving device also utilizes the Perishable Bit in determining which packets to accept and which to discard.

摘要翻译： 本发明提供一种利用高级交换网络协议在诸如多公里的长距离通信的系统和方法。 本发明利用AS分组报头内的称为易变易比特的现有状态比特来减少必须存储在重试缓冲器中的分组数量。 这减少了重试缓冲区的所需大小，并且同时减少了在接收到NAK之后重发关键分组的延迟。 接收设备还利用易逝位来确定哪些分组被接受以及丢弃哪个分组。

公开(公告)号：US20060106967A1

公开(公告)日：2006-05-18

申请号：US11271273

申请日：2005-11-12

申请人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

发明人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/404 ,  H04L49/25 ,  H04L49/252

摘要： The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

公开(公告)号：US20050080976A1

公开(公告)日：2005-04-14

申请号：US10945633

申请日：2004-09-21

申请人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

发明人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

IPC分类号： G06F13/40 ,  H04L12/56 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F13/404 ,  H04L49/25 ,  H04L49/252

摘要： The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

摘要翻译： 本发明一般涉及用于在互连结构内的节点和处理单元之间提供数据路径的通用结构互连系统和方法。 更具体地，提供了一种由主处理器访问的设备，用于将第一总线上的访问扩展到第二总线，第一总线和第二总线各自适于单独连接到多个总线兼容设备中的相应的总线， 包括链路的每个设备，适于在第一总线和链路之间耦合的第一电路，以及适于在链路和第二总线之间耦合的第二电路，第一电路和第二电路各自作为桥接和 可操作以（a）以与第一总线不同的形式串行地发送输出信息，并且第二总线（b）响应于具有一个或多个第一总线的未决总线事务来批准第一总线和第二总线之间的初始交换 表征设备上的目的地的特征，以及（c）允许通过第一总线通信的主处理器在t上独立地寻址不同的可选择的总线兼容设备 他的第二条总线：（i）在第一总线上使用与用于访问第一总线上的装置大致相同类型的寻址的第一总线，以及（ii）在第二总线兼容设备之间没有首先使用第二总线兼容设备 总线。

公开(公告)号：US20070071005A1

公开(公告)日：2007-03-29

申请号：US11235346

申请日：2005-09-26

申请人： David Mayhew ,  Todd Comins

发明人： David Mayhew ,  Todd Comins

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L1/1838 ,  H04L1/1877 ,  H04L47/2416 ,  H04L47/26

摘要： The present invention provides a system and method for utilizing the Advanced Switching network protocol to communicate over long distances, such as multiple kilometers. The present invention utilizes an existing status bit, referred to as the Perishable Bit, within the AS packet header, to reduce the number of packets which must be stored in the retry buffer. This reduces the required size of the retry buffer and simultaneously reduces the latency associated with retransmitting time critical packets after NAKs are received. The receiving device also utilizes the Perishable Bit in determining which packets to accept and which to discard.

摘要翻译： 本发明提供一种利用高级交换网络协议在诸如多公里的长距离通信的系统和方法。 本发明利用AS分组报头内的称为易变易比特的现有状态比特来减少必须存储在重试缓冲器中的分组数量。 这减少了重试缓冲区的所需大小，并且同时减少了在接收到NAK之后重发关键分组的延迟。 接收设备还利用易逝位来确定哪些分组被接受以及丢弃哪个分组。

公开(公告)号：US20050080959A1

公开(公告)日：2005-04-14

申请号：US10945615

申请日：2004-09-21

申请人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

发明人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

IPC分类号： G06F13/40 ,  H04L12/56 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F13/404 ,  H04L49/25 ,  H04L49/252

摘要： The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

公开(公告)号：US20050030963A1

公开(公告)日：2005-02-10

申请号：US10745737

申请日：2003-12-23

申请人： Gary Solomon ,  Edward Butler ,  Joseph Schaefer ,  David Mayhew ,  Todd Comins ,  Lynne Brocco

发明人： Gary Solomon ,  Edward Butler ,  Joseph Schaefer ,  David Mayhew ,  Todd Comins ,  Lynne Brocco

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L47/6205 ,  H04L47/39 ,  H04L47/50 ,  H04L47/56

摘要： A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.

摘要翻译： 描述了排队机制，用于在计算机系统的代理之间管理分组。 排队机制包括包括多个队列寄存器以存储多个分组的有序队列。 排队机构还包括耦合到有序队列的旁路队列，其中，如果排队队列的头部处的分组是延迟的请求，并且由于缺少流量控制信用而被停止，则停顿的分组被移动到旁路队列中。

公开(公告)号：US07809007B2

公开(公告)日：2010-10-05

申请号：US10794067

申请日：2004-03-05

申请人： David Mayhew ,  Karl Meier ,  Nathan Dohm

发明人： David Mayhew ,  Karl Meier ,  Nathan Dohm

IPC分类号： H04L12/28 ,  H04L12/26 ,  H04J3/26

CPC分类号： H04L47/6205

摘要： The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

摘要翻译： 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外，它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息，它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时，输出队列中的数据包将发往拥塞路径，它将违规数据包置于拥塞流队列中，从而允许其他数据包发往 第一个输出端口继续传输。 以这种方式，解决了HOL阻塞问题，而不需要显着增加输出队列数量。

公开(公告)号：US20050195845A1

公开(公告)日：2005-09-08

申请号：US10794067

申请日：2004-03-05

申请人： David Mayhew ,  Karl Meier ,  Nathan Dohm

发明人： David Mayhew ,  Karl Meier ,  Nathan Dohm

IPC分类号： H04L12/28

CPC分类号： H04L47/6205

摘要： The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

摘要翻译： 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外，它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息，它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时，输出队列中的分组将发往拥塞路径，则将违规数据包置于拥塞流队列中，从而允许其他分组发往 第一个输出端口继续传输。 以这种方式，解决了HOL阻塞问题，而不需要显着增加输出队列数量。