公开(公告)号：US07948964B1

公开(公告)日：2011-05-24

申请号：US11956379

申请日：2007-12-14

申请人： Nadim Khlat ,  David Myara ,  Jeremie Rafin

发明人： Nadim Khlat ,  David Myara ,  Jeremie Rafin

IPC分类号： G06F17/00

CPC分类号： H04B1/7073 ,  H04J3/0685 ,  H04W56/0045

摘要： The present invention relates to synchronization circuitry that is used to synchronize an asynchronous received RF message with a transmitted RF message. In one embodiment of the present invention, the synchronization circuitry includes at least one counter, which is used to associate timing of the asynchronous received RF message with a receive count value, and associate timing of the transmitted RF message with a transmit count value. A time delay between occurrence of the receive count value and the transmit count value provides accurate timing for the start of the transmitted RF message.

摘要翻译： 本发明涉及同步电路，其用于将异步接收的RF消息与发射的RF消息同步。 在本发明的一个实施例中，同步电路包括至少一个计数器，其用于将异步接收的RF消息的定时与接收计数值相关联，并将发送的RF消息的定时与发送计数值相关联。 接收计数值的发生与发送计数值之间的时间延迟为发送的RF消息的开始提供准确的定时。

公开(公告)号：US20120121039A1

公开(公告)日：2012-05-17

申请号：US13297490

申请日：2011-11-16

申请人： David Myara ,  Nadim Khlat ,  Jeremie Rafin

发明人： David Myara ,  Nadim Khlat ,  Jeremie Rafin

IPC分类号： H04L25/49 ,  G06F17/16

CPC分类号： G06F7/556 ,  G06F1/0307 ,  H03F1/0227 ,  H03M7/04

摘要： Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.

摘要翻译： 公开了具有选择第一部件或第二部件中较大者的最大值电路的坐标旋转数字计算机（CORDIC）。 最小值电路选择作为第一分量或第二​​分量中较小的一个的最小操作数。 还包括N个旋转器级，每个对应于N个预定向量中的唯一一个，N个旋转器级中的每一个具有第一乘法电路，以将最大操作数乘以预定向量的余弦系数，以输出第一旋转分量， 第二乘法电路，用于将最小操作数乘以预定向量的正弦系数以输出第二旋转分量;以及加法器电路，用于将第一旋转分量与第二旋转分量相加以输出N个结果中的一个，以及最大值电路 用于输出N个结果中的最大值。

公开(公告)号：US08085754B1

公开(公告)日：2011-12-27

申请号：US13071139

申请日：2011-03-24

申请人： Nadim Khlat ,  David Myara ,  Jeremie Rafin

发明人： Nadim Khlat ,  David Myara ,  Jeremie Rafin

IPC分类号： G06F17/00

CPC分类号： H04B1/7073 ,  H04J3/0685 ,  H04W56/0045

摘要： The present invention relates to synchronization circuitry that is used to synchronize an asynchronous received RF message with a transmitted RF message. In one embodiment of the present invention, the synchronization circuitry includes at least one counter, which is used to associate timing of the asynchronous received RF message with a receive count value, and associate timing of the transmitted RF message with a transmit count value. A time delay between occurrence of the receive count value and the transmit count value provides accurate timing for the start of the transmitted RF message.

公开(公告)号：US08180384B1

公开(公告)日：2012-05-15

申请号：US11777663

申请日：2007-07-13

申请人： Nadim Khlat ,  David Myara

发明人： Nadim Khlat ,  David Myara

IPC分类号： H04J3/06

CPC分类号： H04W56/0045

摘要： An RF transmitter that, during a transmission session, transmits multiple data slices, which are synchronized to each other by a transmit counter. Typically, the time between transmission of consecutive data slices is constant; however, to synchronize the transmission session with a base station, the time between transmission of consecutive data slices may be occasionally adjusted. By using the transmit counter to synchronize data transmissions, effects of uncompensated latencies or variances in latencies may be reduced or eliminated.

摘要翻译： 在发射会话期间，发射多个数据片段的RF发射机，其由发射计数器彼此同步。 通常，连续数据切片传输之间的时间是恒定的; 然而，为了使传输会话与基站同步，可能偶尔调整连续数据片的传输之间的时间。 通过使用发送计数器来同步数据传输，可以减少或消除未补偿延迟或延迟方面的影响。

公开(公告)号：US08189707B1

公开(公告)日：2012-05-29

申请号：US12117282

申请日：2008-05-08

申请人： Nadim Khlat ,  David Myara

发明人： Nadim Khlat ,  David Myara

IPC分类号： H04L27/02 ,  H04L27/04 ,  H04L25/06 ,  H04B1/38 ,  H03D1/00

CPC分类号： H03G3/3042 ,  H04B2001/0416

摘要： The present invention relates to estimating a direct current (DC) offset of a radio frequency (RF) receiver when an estimated amplitude of a continuous-transmission amplitude-modulated (AM) RF signal is below a first threshold and when the RF receiver is not receiving an RF input signal. The estimated DC offset of the RF receiver may be used to improve RF receiver performance, particularly over temperature and supply voltage variations. Estimating the DC offset of the RF receiver when the estimated instantaneous amplitude of the continuous-transmission AM RF signal is below the first threshold may minimize errors in the estimated DC offset.

摘要翻译： 本发明涉及当连续发射幅度调制（AM）RF信号的估计振幅低于第一阈值时以及当RF接收机不是时，估计射频（RF）接收机的直流（DC）偏移 接收RF输入信号。 RF接收机的估计直流偏移可用于提高RF接收机性能，特别是在温度和电源电压变化方面。 当连续传输AM RF信号的估计瞬时幅度低于第一阈值时，估计RF接收机的DC偏移可以使估计的DC偏移中的误差最小化。

公开(公告)号：US08139540B2

公开(公告)日：2012-03-20

申请号：US11571099

申请日：2004-07-02

申请人： Nadim Khlat ,  David Myara

发明人： Nadim Khlat ,  David Myara

IPC分类号： H04W36/00 ,  H04B7/216

CPC分类号： H04W88/06

摘要： An arrangement and method for discontinuous software FDD monitoring during TDD call allows removal of a conventional external notch filter in a dual mode WCDMA and PCS/DCS handset. The WCDMA RX frame is allowed to have a few slots corrupted by the PCS/DCS transmitter noise during DCS transmission, and a scheme is used to recover the required information by not considering the corrupted slots. Due to the fact that during WCDMA FDD RX monitoring, the processing required is performed in stages, and since the information that is measured during a WCDMA frame is repeated in every frame, the scheme of the invention is based on the idea that if a given slot is corrupted in a WCDMA frame, in the next WCDMA frame the slot will be no more corrupted due to the difference in timing between the PCS/DCS transmitter protocol and the WCDMA timing protocol.

摘要翻译： 在TDD呼叫期间用于不连续软件FDD监视的布置和方法允许在双模WCDMA和PCS / DCS手机中去除传统的外部陷波滤波器。 在DCS传输期间，允许WCDMA RX帧具有被PCS / DCS发射机噪声损坏的几个时隙，并且使用一种方案来通过不考虑损坏的时隙来恢复所需的信息。 由于在WCDMA FDD RX监视期间，所需的处理是分阶段执行的，并且由于在每帧中重复在WCDMA帧期间测量的信息，所以本发明的方案基于以下思想：如果给定 时隙在WCDMA帧中被破坏，在下一个WCDMA帧中，由于PCS / DCS发射机协议和WCDMA定时协议之间的定时差异，该时隙将不再被破坏。

公开(公告)号：US08005441B1

公开(公告)日：2011-08-23

申请号：US12117269

申请日：2008-05-08

申请人： Nadim Khlat ,  David Myara

发明人： Nadim Khlat ,  David Myara

IPC分类号： H04B1/04 ,  H01Q11/12

CPC分类号： H03G3/3042 ,  H04B2001/0416

摘要： The present invention relates to estimating a direct current (DC) offset of a power detection circuit when an estimated instantaneous amplitude of a continuous-transmission amplitude-modulated (AM) radio frequency (RF) signal is below a first threshold. The power detection circuit may be used to estimate an average output power associated with the continuous-transmission AM RF signal. The estimated average output power may be used as part of a feedback system to regulate the average output power. The estimated DC offset of the power detection circuit may be used to improve the estimate of the average output power, particularly over temperature and supply voltage variations. Estimating the DC offset of the power detection circuit when the estimated instantaneous amplitude of the continuous-transmission AM RF signal is below the first threshold may minimize errors in the estimated DC offset.

摘要翻译： 本发明涉及当连续发射幅度调制（AM）射频（RF）信号的估计瞬时幅度低于第一阈值时估计功率检测电路的直流偏移。 功率检测电路可以用于估计与连续发送AM RF信号相关联的平均输出功率。 估计的平均输出功率可以用作反馈系统的一部分，以调节平均输出功率。 功率检测电路的估计的DC偏移可以用于改善平均输出功率的估计，特别是在温度和电源电压变化方面。 当估计的连续发送AM RF信号的瞬时幅度低于第一阈值时，估计功率检测电路的DC偏移可以使估计的DC偏移中的误差最小化。

公开(公告)号：US07724805B1

公开(公告)日：2010-05-25

申请号：US11470340

申请日：2006-09-06

申请人： Nadim Khlat ,  David Myara

发明人： Nadim Khlat ,  David Myara

IPC分类号： H04L27/36 ,  H04B1/00

CPC分类号： H04W52/52 ,  H04B17/327 ,  H04B2201/70707 ,  H04J13/004

摘要： A system and method are provided for quickly measuring the Root Mean Square (RMS) value of digital quadrature signals (I, Q) input to a Wideband Code Division Multiple Access (W-CDMA) transmitter. In general, in a W-CDMA transmitter such as that in a Universal Mobile Telecommunications System (UMTS), multiple channels are combined to provide the digital quadrature signal (I, Q) input to the transmitter. The RMS value of the digital quadrature signal (I, Q) may be determined using a number of consecutive samples of the digital quadrature signal (I, Q) over a period corresponding to mutually orthogonal segments of the spreading codes used for the transmitted channels. As a result of the mutual orthogonality of the segments of the spreading codes, a residual error of the RMS measurement is equal to zero, thereby providing an accurate RMS measurement in much less time than required by traditional RMS measurement schemes.

摘要翻译： 提供了一种用于快速测量输入到宽带码分多址（W-CDMA）发射机的数字正交信号（I，Q）的均方根（RMS）值的系统和方法。 通常，在诸如通用移动电信系统（UMTS）中的W-CDMA发射机中，组合多个信道以提供输入到发射机的数字正交信号（I，Q）。 数字正交信号（I，Q）的RMS值可以在对应于用于发送信道的扩展码的相互正交的段的周期内使用数字正交信号（I，Q）的连续采样数来确定。 作为扩展码段的互相正交性的结果，RMS测量的残余误差等于零，从而在比传统RMS测量方案所要求的时间少得多的时间内提供精确的RMS测量。

公开(公告)号：US08782107B2

公开(公告)日：2014-07-15

申请号：US13297490

申请日：2011-11-16

申请人： David Myara ,  Nadim Khlat ,  Jérémie Rafin

发明人： David Myara ,  Nadim Khlat ,  Jérémie Rafin

IPC分类号： G06F7/00 ,  G06F7/38

CPC分类号： G06F7/556 ,  G06F1/0307 ,  H03F1/0227 ,  H03M7/04

摘要： Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.

摘要翻译： 公开了具有选择第一部件或第二部件中较大者的最大值电路的坐标旋转数字计算机（CORDIC）。 最小值电路选择作为第一分量或第二​​分量中较小的一个的最小操作数。 还包括N个旋转器级，每个对应于N个预定向量中的唯一一个，N个旋转器级中的每一个具有第一乘法电路，以将最大操作数乘以预定向量的余弦系数，以输出第一旋转分量， 第二乘法电路，用于将最小操作数乘以预定向量的正弦系数以输出第二旋转分量;以及加法器电路，用于将第一旋转分量与第二旋转分量相加以输出N个结果中的一个，以及最大值电路 用于输出N个结果中的最大值。

公开(公告)号：US20090103489A1

公开(公告)日：2009-04-23

申请号：US11571099

申请日：2004-07-02

申请人： Nadim Khlat ,  David Myara

发明人： Nadim Khlat ,  David Myara

IPC分类号： H04W36/00 ,  H04B7/216

CPC分类号： H04W88/06

摘要： An arrangement and method for discontinuous software FDD monitoring during TDD call allows removal of a conventional external notch filter in a dual mode WCDMA and PCS/DCS handset. The WCDMA RX frame is allowed to have a few slots corrupted by the PCS/DCS transmitter noise during DCS transmission, and a scheme is used to recover the required information by not considering the corrupted slots. Due to the fact that during WCDMA FDD RX monitoring, the processing required is performed in stages, and since the information that is measured during a WCDMA frame is repeated in every frame, the scheme of the invention is based on the idea that if a given slot is corrupted in a WCDMA frame, in the next WCDMA frame the slot will be no more corrupted due to the difference in timing between the PCS/DCS transmitter protocol and the WCDMA timing protocol.

摘要翻译： 在TDD呼叫期间用于不连续软件FDD监视的布置和方法允许在双模WCDMA和PCS / DCS手机中去除传统的外部陷波滤波器。 在DCS传输期间，允许WCDMA RX帧具有被PCS / DCS发射机噪声损坏的几个时隙，并且使用一种方案来通过不考虑损坏的时隙来恢复所需的信息。 由于在WCDMA FDD RX监视期间，所需的处理是分阶段执行的，并且由于在每帧中重复在WCDMA帧期间测量的信息，所以本发明的方案基于以下思想：如果给定 时隙在WCDMA帧中被破坏，在下一个WCDMA帧中，由于PCS / DCS发射机协议和WCDMA定时协议之间的定时差异，该时隙将不再被破坏。