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    ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS
    3.
    发明申请
    ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS 审中-公开
    具有各种闪存存储器的电子数据闪存卡

    公开(公告)号：US20080071978A1

    公开(公告)日：2008-03-20

    申请号：US11929847

    申请日：2007-10-30

    申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

    发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

    摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

    摘要翻译： 电子数据闪存卡可由主机访问，并且包括连接到存储数据文件的闪存设备的处理单元，以及被激活以便与主计算机建立通信的输入 - 输出接口电路。 在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。 闪速存储器控制器包括用于将由主计算机发送的逻辑地址转换成与闪存器件的扇区相关联的物理地址的索引。 该索引由参考来自各种查找表中的值和存储在闪存设备中的有效数据的仲裁逻辑控制。 闪存控制器还包括先进先出单元（FIFO），用于在后台进程中回收闪速存储器件的过时扇区，使得它们可用于重新编程。

    SRAM cache and flash micro-controller with differential packet interface
    10.
    发明授权
    SRAM cache and flash micro-controller with differential packet interface 失效
    具有差分数据包接口的SRAM缓存和闪存微控制器

    公开(公告)号：US07707354B2

    公开(公告)日：2010-04-27

    申请号：US11876251

    申请日：2007-10-22

    申请人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen

    发明人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0866 ,  G06F2212/2022 ,  G06F2212/2515

    摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.

    摘要翻译： 闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。 引导完成后，SRAM缓冲区还可以作为闪存数据缓存。 缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。 外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。 引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。 闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。 帧，分组和编码时钟处理也由串行接口执行。