公开(公告)号：US08228958B1

公开(公告)日：2012-07-24

申请号：US11584360

申请日：2006-10-20

申请人： David R. Stiles ,  Siegfried Luft ,  Lawrence Ong ,  James C. Pang

发明人： David R. Stiles ,  Siegfried Luft ,  Lawrence Ong ,  James C. Pang

IPC分类号： H04J3/12

CPC分类号： H04J3/085 ,  H04L12/43 ,  Y10S370/907

摘要： A ring network element and the ring network architectures it enables. According to one embodiment of the invention, a single network element includes a full TDM cross-connect and a multiple ring unit. The full TDM cross-connect is coupled to very line card slot in the single network element with the same amount of bandwidth connection. In addition, the full TDM cross-connect is programmable on an STS-1 basis. The multiple ring unit allows for the simultaneous support of multiple TDM rings.

摘要翻译： 环网元件和环网网络架构使其实现。 根据本发明的一个实施例，单个网元包括全TDM交叉连接和多环单元。 完整的TDM交叉连接与相同数量的带宽连接的单个网络中的非常线卡插槽相连。 此外，完整的TDM交叉连接可以基于STS-1进行编程。 多环单元允许同时支持多个TDM环。

公开(公告)号：US07158540B1

公开(公告)日：2007-01-02

申请号：US09823871

申请日：2001-03-30

申请人： David R. Stiles ,  Siegfried Luft ,  Lawrence Ong ,  James C. Pang

发明人： David R. Stiles ,  Siegfried Luft ,  Lawrence Ong ,  James C. Pang

IPC分类号： H04J3/00

CPC分类号： H04J3/085 ,  H04L12/43 ,  Y10S370/907

摘要： A ring network element and the ring network architectures it enables. According to one embodiment of the invention, a single network element includes a full TDM cross-connect and a multiple ring unit. The full TDM cross-connect is coupled to every line card slot in the single network element with the same amount of bandwidth connection. In addition, the full TDM cross-connect is programmable on an STS-1 basis. The multiple ring unit allows for the simultaneous support of multiple TDM rings.

摘要翻译： 环网元件和环网网络架构使其实现。 根据本发明的一个实施例，单个网元包括全TDM交叉连接和多环单元。 完整的TDM交叉连接与相同数量的带宽连接耦合到单个网络单元中的每个线路卡插槽。 此外，完整的TDM交叉连接可以基于STS-1进行编程。 多环单元允许同时支持多个TDM环。

公开(公告)号：US6021471A

公开(公告)日：2000-02-01

申请号：US340176

申请日：1994-11-15

申请人： David R. Stiles ,  Teresa A. Roth

发明人： David R. Stiles ,  Teresa A. Roth

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0855 ,  G06F12/0811 ,  G06F12/0864

摘要： A cache controller for a system having first and second level cache memories. The cache controller has multiple stage address and data pipelines. A look-up system allows concurrent look-up of tag addresses in the first and second level caches using the address pipeline. The multiple stages allow a miss in the first level cache to be moved to the second stage so that the latency does not slow the look-up of a next address in the first level cache. A write data pipeline allows the look-up of data being written to the first level cache for current read operations. A stack of registers coupled to the address pipeline is used to perform multiple line replacements of the first level cache memory without interfering with current first level cache memory look-ups.

摘要翻译： 一种用于具有第一和第二级高速缓冲存储器的系统的高速缓存控制器。 缓存控制器具有多级地址和数据管道。 查找系统允许使用地址管道在第一和第二级高速缓存中同时查找标签地址。 多级允许将第一级高速缓存中的未命中移动到第二级，使得等待时间不会降低第一级高速缓存中下一地址的查找速度。 写数据流水线允许将数据的查找写入到第一级高速缓存用于当前读操作。 耦合到地址管线的一堆寄存器用于执行第一级高速缓冲存储器的多行替代，而不会干扰当前的第一级高速缓冲存储器查找。

公开(公告)号：US5511175A

公开(公告)日：1996-04-23

申请号：US326409

申请日：1994-10-20

申请人： John G. Favor ,  Korbin Van Dyke ,  David R. Stiles

发明人： John G. Favor ,  Korbin Van Dyke ,  David R. Stiles

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3812 ,  G06F9/3804 ,  G06F9/3844 ,  G06F9/3863

摘要： The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache. Upon such a detection, that entry in the instruction cache is invalidated, and the corresponding entry in the branch prediction cache is invalidated. A subsequent attempt to use an instruction in the branch prediction cache which has been invalidated will detect that it is not valid, and will instead go to main memory to fetch the instruction, where it has been modified.

摘要翻译： 本发明提供了当执行的指令尝试改变这样的指令（“存储到指令流”）时更新分支预测高速缓存中的两个指令和最近提供给来自高速缓存的指令流水线的指令。 分支预测高速缓存（BPC）包括识别导致分支的指令的地址的标签，在每个分支指令的最后出现时被分支的目标地址的记录以及从该目标开始的前几个指令的副本 地址。 提供单独的指令高速缓存用于指令的正常执行，并且从系统总线写入分支预测高速缓存的所有指令也必须存储在指令高速缓存中。 指令高速缓存监视系统总线以尝试写入指令高速缓存中包含的指令的地址。 在这种检测中，指令高速缓存中的该条目无效，并且分支预测高速缓存中的相应条目无效。 随后尝试使用已经无效的分支预测高速缓存中的指令将检测到它无效，并且将转到主存储器以获取已经被修改的指令。

公开(公告)号：US5442757A

公开(公告)日：1995-08-15

申请号：US25439

申请日：1993-03-03

申请人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John G. Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

发明人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John G. Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/318 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F11/36 ,  G06F15/78 ,  G06F15/16

CPC分类号： G06F11/3648 ,  G06F15/8053 ,  G06F9/30003 ,  G06F9/30018 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/34 ,  G06F9/3555 ,  G06F9/38 ,  G06F9/3804 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3869 ,  G06F9/3885

摘要： A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

摘要翻译： 流水线控制系统分布在处理器（10）中的功能单元（15,17,20,25）上。 解码器逻辑（12）向功能单元发出每个具有关联标签的操作，最多允许n个操作被显示。 单元执行操作并将终止信息报告回解码器逻辑，但不能不可逆转地改变机器的状态。 基于终止信息，解码器逻辑依次退出正常终止的操作。 如果操作异常终止，则解码器逻辑指示单元退出包括并晚于异常终止的操作的那些操作。

公开(公告)号：US5093778A

公开(公告)日：1992-03-03

申请号：US485307

申请日：1990-02-26

申请人： John G. Favor ,  David R. Stiles ,  Korbin Van Dyke ,  Walstein B. Smith, III

发明人： John G. Favor ,  David R. Stiles ,  Korbin Van Dyke ,  Walstein B. Smith, III

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3844

摘要： The present invention provides an improved branch prediction cache (BPC) structure that combines various separate structures into one integrated structure. In conjunction with doing this, the present invention is able to share significant portions of hardware cost and design complexity overhead. As a result, the cost-performance trade-off for implementing dynamic branch prediction for target address, branch direction, and target instructions aspects of branches shifts to where "full" branch prediction is now more practical.

摘要翻译： 本发明提供一种将各种单独的结构组合为一个集成结构的改进的分支预测高速缓存（BPC）结构。 结合这一点，本发明能够共享硬件成本和设计复杂度开销的重要部分。 因此，用于实现分支目标地址，分支方向和分支方向以及目标指令方面的动态分支预测的成本 - 性能折衷转向现在更加实用的“全”分支预测。

公开(公告)号：US5905997A

公开(公告)日：1999-05-18

申请号：US732951

申请日：1996-10-17

申请人： David R. Stiles

发明人： David R. Stiles

IPC分类号： G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0864

摘要： Multiple banks associated with a multiple set associative cache are stored in a single chip, reducing the number of SRAMs required. Certain status information for the second level (L2) cache is stored with the status information of the first level cache. This enhances the speed of operations by avoiding a status look-up and modification in the L2 cache during a write operation. In addition, the L2 cache tag address and status bits are stored in a portion of one bank of the L2 data RAMs, further reducing the number of SRAMs required. Finally, the present invention also provides local read-write storage for use by the processor by reserving a number of L2 cache lines.

摘要翻译： 与多组关联高速缓存相关联的多个存储体存储在单个芯片中，减少了所需的SRAM数量。 第二级（L2）缓存的某些状态信息与第一级高速缓存的状态信息一起存储。 这通过在写入操作期间避免在L2高速缓存中的状态查找和修改来提高操作速度。 另外，二级缓存标签地址和状态位存储在L2数据RAM的一组的一部分中，进一步减少了所需的SRAM数量。 最后，本发明还提供了由处理器通过预留多个L2高速缓存行来使用的本地读写存储。

公开(公告)号：US5881265A

公开(公告)日：1999-03-09

申请号：US463459

申请日：1995-06-05

申请人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John Gregory Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

发明人： Harold L. McFarland ,  David R. Stiles ,  Korbin S. Van Dyke ,  Shrenik Mehta ,  John Gregory Favor ,  Dale R. Greenley ,  Robert A. Cargnoni

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/318 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F11/36 ,  G06F15/78

CPC分类号： G06F11/3648 ,  G06F15/8053 ,  G06F9/30003 ,  G06F9/30018 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/34 ,  G06F9/3555 ,  G06F9/38 ,  G06F9/3804 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3869 ,  G06F9/3885

摘要： A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

公开(公告)号：US5649137A

公开(公告)日：1997-07-15

申请号：US582294

申请日：1996-01-03

申请人： John G. Favor ,  Korbin Van Dyke ,  David R. Stiles

发明人： John G. Favor ,  Korbin Van Dyke ,  David R. Stiles

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3812 ,  G06F9/3844

摘要： The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache. Upon such a detection, that entry in the instruction cache is invalidated, and the corresponding entry in the branch prediction cache is invalidated. A subsequent attempt to use an instruction in the branch prediction cache which has been invalidated will detect that it is not valid, and will instead go to main memory to fetch the instruction, where it has been modified.

摘要翻译： 本发明提供了当执行的指令尝试改变这样的指令（“存储到指令流”）时更新分支预测高速缓存中的两个指令和最近提供给来自高速缓存的指令流水线的指令。 分支预测高速缓存（BPC）包括识别导致分支的指令的地址的标签，在每个分支指令的最后出现时被分支的目标地址的记录以及从该目标开始的前几个指令的副本 地址。 提供单独的指令高速缓存用于指令的正常执行，并且从系统总线写入分支预测高速缓存的所有指令也必须存储在指令高速缓存中。 指令高速缓存监视系统总线以尝试写入指令高速缓存中包含的指令的地址。 在这种检测中，指令高速缓存中的该条目无效，并且分支预测高速缓存中的相应条目无效。 随后尝试使用已经无效的分支预测高速缓存中的指令将检测到它无效，并且将转到主存储器以获取已经被修改的指令。

公开(公告)号：US5327547A

公开(公告)日：1994-07-05

申请号：US954441

申请日：1992-09-30

申请人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

发明人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3848

摘要： An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

摘要翻译： 利用混合缓存结构的改进的分支预测高速缓存（BPC）方案。 BPC提供两级分支信息缓存。 完全关联的第一级BPC是浅而宽的结构（36个32字节的条目），其缓存有限数量的分支指令的全部预测信息。 第二个直接映射级别BPC是一个深而窄的结构（256个2字节条目），它仅缓存部分预测信息，但对于大量的分支指令则是这样做的。 当每个分支指令被取出和解码时，其地址用于在两个分支预测高速缓存中执行并行查找。