公开(公告)号：US20060095884A1

公开(公告)日：2006-05-04

申请号：US11298717

申请日：2005-12-12

申请人： David Skoll ,  Terry Ludlow ,  Julia Elvidge

发明人： David Skoll ,  Terry Ludlow ,  Julia Elvidge

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06T7/001 ,  G06F17/5081 ,  G06T7/0006 ,  G06T7/97 ,  G06T2200/24 ,  G06T2200/32 ,  G06T2207/30148

摘要： A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.

公开(公告)号：US06453063B1

公开(公告)日：2002-09-17

申请号：US09238435

申请日：1999-01-28

申请人： Michael Phaneuf ,  Dick James ,  Julia Elvidge ,  Pierrette Breton ,  Terry Ludlow ,  David Skoll ,  Bryan Socransky ,  Louise Weaver ,  Ray Haythornthwaite

发明人： Michael Phaneuf ,  Dick James ,  Julia Elvidge ,  Pierrette Breton ,  Terry Ludlow ,  David Skoll ,  Bryan Socransky ,  Louise Weaver ,  Ray Haythornthwaite

IPC分类号： G06K900

CPC分类号： G01N23/04 ,  G01N23/2258 ,  H01J2237/221 ,  H01J2237/226 ,  H01J2237/28

摘要： A method of imaging an integrated circuit using a focused ion beam system is presented. According to the method an integrated circuit is imaged in plan-view using a focused ion beam system. Circuit information is then extracted absent processing. In another embodiment, a method and system for imaging an entire IC automatically without removing the IC from the imaging system and requiring minimal operator intervention is presented. The method employs a focused ion beam system to image an exposed layer of an integrated circuit and then to etch a portion of the exposed layer in situ. Imaging and etching are repeated until substantially the entire integrated circuit is imaged. A processor is used to assemble the layers into a three-dimensional topography of the integrated circuit. Because of known relationships between layers, the mosaicing is facilitated and the final topography is more reliable than those produced by currently known computer implemented methods.

摘要翻译： 提出了一种使用聚焦离子束系统对集成电路进行成像的方法。 根据该方法，使用聚焦离子束系统在平面图中成像集成电路。 然后在没有处理的情况下提取电路信息。 在另一个实施例中，提出了一种用于自动成像整个IC而不从成像系统中移除IC并且需要最小的操作者干预的方法和系统。 该方法采用聚焦离子束系统来对集成电路的暴露层进行成像，然后原位蚀刻暴露层的一部分。 重复成像和蚀刻，直到基本上整个集成电路被成像。 处理器用于将层组装成集成电路的三维形貌。 由于层之间已知的关系，便于马赛克化，并且最终的形貌比目前已知的计算机实现的方法产生的形状更可靠。