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    Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method
    1.
    发明授权
    Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method 失效
    集成电路设计和制造方法以及根据该方法设计集成电路的装置

    公开(公告)号：US5689432A

    公开(公告)日：1997-11-18

    申请号：US373695

    申请日：1995-01-17

    申请人： David T. Blaauw ,  Robert L. Maziasz ,  Joseph W. Norton ,  Larry G. Jones ,  Mohankumar Guruswamy

    发明人： David T. Blaauw ,  Robert L. Maziasz ,  Joseph W. Norton ,  Larry G. Jones ,  Mohankumar Guruswamy

    IPC分类号： G06F17/50 ,  H01L27/02

    CPC分类号： H01L27/0207 ,  G06F17/505 ,  G06F17/5068

    摘要： A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plurality of interconnected logic gate functions to duplicate the operation of the BCM. The gates in the data file are then assigned a specific Vdd and ground rail size, a specific drive strength for speed considerations, and a cell pitch or height to optimize physical layout, in any order. The result in a physical design file which may be used to form masks and integrated circuits having optimized speed and optimized circuit area in a short design cycle.

    摘要翻译： 集成电路的设计方法涉及四步法。 首先，读取行为电路模型（BCM），其包含识别集成电路（IC）的逻辑运算的分配语句。 将BCM转换为描述多个互连的逻辑门功能以复制BCM的操作的数据文件。 然后，以任何顺序，将数据文件中的门分配特定的Vdd和地面轨道尺寸，速度考虑的特定驱动强度以及单元间距或高度来优化物理布局。 物理设计文件的结果可以用于形成具有优化速度的掩模和集成电路，并在短的设计周期内优化电路面积。

    Method and apparatus for designing an integrated circuit
    2.
    发明授权
    Method and apparatus for designing an integrated circuit 失效
    用于设计集成电路的方法和装置

    公开(公告)号：US5666288A

    公开(公告)日：1997-09-09

    申请号：US426211

    申请日：1995-04-21

    申请人： Larry G. Jones ,  David T. Blaauw ,  Robert L. Maziasz ,  Mohan Guruswamy

    发明人： Larry G. Jones ,  David T. Blaauw ,  Robert L. Maziasz ,  Mohan Guruswamy

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/505

    摘要： A method and apparatus for designing and manufacturing integrated circuits (ICs) involves providing an initial library of IC cells (106) and a behavioral circuit model (100) in order to create a gate schematic netlist (102). The gate schematic netlist (102) is optimized by changing individual transistor sizes, power rail sizes, cell pitch, and the like in a step (103). Once the optimization has occurred, the initial library can no longer be used to place and route the IC. Therefore, a hybrid logic cell library is created from the gate schematic netlist (102) via a step (105). This hybrid library and the above optimizations provides a placed and routed IC via a step (126) in a short design cycle while optimizing performance of the IC.

    摘要翻译： 用于设计和制造集成电路（IC）的方法和装置涉及提供IC单元（106）的初始库和行为电路模型（100），以便创建门逻辑网络表（102）。 通过在步骤（103）中改变单个晶体管尺寸，电源轨尺寸，电池间距等来优化门逻辑示意图网表（102）。 一旦发生优化，初始库将不能再用于放置和路由IC。 因此，经由步骤（105）从门逻辑示意图网表（102）创建混合逻辑单元库。 该混合库和上述优化通过步骤（126）在短的设计周期中提供放置和布线的IC，同时优化IC的性能。

    Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized
    3.
    发明授权
    Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized 失效
    用于集成电路的逻辑门尺寸优化处理，从而在优化电路面积的同时提高电路速度

    公开(公告)号：US5619418A

    公开(公告)日：1997-04-08

    申请号：US390210

    申请日：1995-02-16

    申请人： David T. Blaauw ,  Joseph W. Norton ,  Larry G. Jones ,  Susanta Misra ,  R. Iris Bahar

    发明人： David T. Blaauw ,  Joseph W. Norton ,  Larry G. Jones ,  Susanta Misra ,  R. Iris Bahar

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity=.DELTA.speed/.DELTA.area) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area. The above process continues iteratively until no out-of-specification circuit paths are found.

    摘要翻译： 集成电路在设计时必须遵守时序约束，同时尽量减少电路面积。 为了在达到近似最佳电路表面积的同时遵循定时规范，使用迭代过程，其通过从存储器存储逻辑门库访问逻辑门来选择性地增加逻辑门大小。 电路表示与电路路径的时序约束一起读取。 处理电路中的每个电路路径以找到其实际的电路路径延迟。 在电路中选择最不符合规范的电路路径（在速度方面），并且在最规范的电路路径中对每个逻辑门执行灵敏度计算。 具有最大灵敏度（灵敏度= DELTA速度/ DELTA面积）的电路路径中的逻辑门的大小通过访问库中较大的门而增加，以便以面积为代价来提高速度。 上述过程继续进行，直到找不到超出规范的电路路径。

    Simultaneous vision emulation for fitting of corrective multifocal contact lenses
    5.
    发明授权
    Simultaneous vision emulation for fitting of corrective multifocal contact lenses 有权
    用于矫正多焦点隐形眼镜的同时视觉仿真

    公开(公告)号：US07455403B2

    公开(公告)日：2008-11-25

    申请号：US11463053

    申请日：2006-08-08

    申请人： Larry G. Jones ,  John R. Buch

    发明人： Larry G. Jones ,  John R. Buch

    IPC分类号： G02C7/04 ,  A61B3/10

    CPC分类号： A61B3/0285 ,  A61B3/04

    摘要： An emulator including a beam splitter for splitting incoming light energy into a first component directed along a first optical path, and a second component directed along a second optical path distinct from the first optical path. The emulator includes a first receptacle positioned to pass light energy directed along only the first optical path. The first receptacle is capable of receiving an add lens for providing an add power. A beam combiner is positioned to combine light energy of the second component with light energy of the first component that has passed the first receptacle, i.e. to have the add power applied, and to direct the combined light energy along a common optical path. Additional receptacles are provided that are capable of receiving a sphere and/or a cylindrical lens in position to pass the combined light energy traveling along the common optical path.

    摘要翻译： 一种仿真器，包括用于将入射光能分解成沿着第一光路指向的第一分量的分束器，以及沿着与第一光路不同的第二光路指向的第二分量。 仿真器包括第一插座，其被定位成传递仅沿着第一光路指向的光能。 第一容器能够接收用于提供附加功率的附加镜头。 光束组合器被定位成将第二部件的光能与已经通过第一插座的第一部件的光能组合，即具有施加的附加功率，并沿着公共光路引导组合的光能。 提供了附加的插座，其能够接收球体和/或柱面透镜在适当位置以通过沿着公共光路行进的组合光能量。

    CONTACT LENSES WITH LIGHT BLOCKING RINGS
    9.
    发明申请
    CONTACT LENSES WITH LIGHT BLOCKING RINGS 有权
    带光圈环的接触镜

    公开(公告)号：US20080002147A1

    公开(公告)日：2008-01-03

    申请号：US11427375

    申请日：2006-06-29

    申请人： James W. Haywood ,  Larry G. Jones ,  Jerry W. Dukes

    发明人： James W. Haywood ,  Larry G. Jones ,  Jerry W. Dukes

    IPC分类号： G02C7/04

    CPC分类号： G02C7/04 ,  G02C7/102 ,  G02C7/105

    摘要： The invention provides contact lenses that substantially block either or both UV and blue light from entering the lens wearer's pupil by providing multiple concentric areas of certain materials that decrease or substantially eliminate the UV and blue light transmission. The lenses of the invention accomplish the light blocking without degrading the lens wearer's vision.

    摘要翻译： 本发明提供隐形眼镜，其通过提供减少或基本上消除UV和蓝光透射的某些材料的多个同心区域，基本上阻挡紫外线和蓝光中的一者或两者进入镜片佩戴者的瞳孔。 本发明的镜片能够实现遮光，而不会降低镜片佩戴者的视力。

    Multifocal ophthalmic lenses
    10.
    发明授权
    Multifocal ophthalmic lenses 有权
    多焦点眼科镜片

    公开(公告)号：US06986578B2

    公开(公告)日：2006-01-17

    申请号：US10354401

    申请日：2003-01-30

    申请人： Larry G. Jones

    发明人： Larry G. Jones

    IPC分类号： G02C7/04

    CPC分类号： G02C7/048 ,  G02C7/041 ,  G02C7/042 ,  G02C7/045 ,  G02C2202/22

    摘要： The invention provides lenses for correcting presbyopia in which the near vision segments interfere at least about 50% less with distance vision than do the near vision segments in conventional contact lenses.

    摘要翻译： 本发明提供了用于校正远视视力的近视眼段与常规隐形眼镜中的近视力段相比至少远远远视力干扰至少约50％的镜片。