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公开(公告)号：US5666288A
公开(公告)日：1997-09-09
申请号：US426211
申请日：1995-04-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： A method and apparatus for designing and manufacturing integrated circuits (ICs) involves providing an initial library of IC cells (106) and a behavioral circuit model (100) in order to create a gate schematic netlist (102). The gate schematic netlist (102) is optimized by changing individual transistor sizes, power rail sizes, cell pitch, and the like in a step (103). Once the optimization has occurred, the initial library can no longer be used to place and route the IC. Therefore, a hybrid logic cell library is created from the gate schematic netlist (102) via a step (105). This hybrid library and the above optimizations provides a placed and routed IC via a step (126) in a short design cycle while optimizing performance of the IC.
摘要翻译： 用于设计和制造集成电路（IC）的方法和装置涉及提供IC单元（106）的初始库和行为电路模型（100），以便创建门逻辑网络表（102）。 通过在步骤（103）中改变单个晶体管尺寸，电源轨尺寸，电池间距等来优化门逻辑示意图网表（102）。 一旦发生优化，初始库将不能再用于放置和路由IC。 因此，经由步骤（105）从门逻辑示意图网表（102）创建混合逻辑单元库。 该混合库和上述优化通过步骤（126）在短的设计周期中提供放置和布线的IC，同时优化IC的性能。
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2.发明授权
公开(公告)号：US5689432A
公开(公告)日：1997-11-18
申请号：US373695
申请日：1995-01-17
CPC分类号： H01L27/0207 , G06F17/505 , G06F17/5068
摘要： A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plurality of interconnected logic gate functions to duplicate the operation of the BCM. The gates in the data file are then assigned a specific Vdd and ground rail size, a specific drive strength for speed considerations, and a cell pitch or height to optimize physical layout, in any order. The result in a physical design file which may be used to form masks and integrated circuits having optimized speed and optimized circuit area in a short design cycle.
摘要翻译： 集成电路的设计方法涉及四步法。 首先，读取行为电路模型（BCM），其包含识别集成电路（IC）的逻辑运算的分配语句。 将BCM转换为描述多个互连的逻辑门功能以复制BCM的操作的数据文件。 然后，以任何顺序，将数据文件中的门分配特定的Vdd和地面轨道尺寸，速度考虑的特定驱动强度以及单元间距或高度来优化物理布局。 物理设计文件的结果可以用于形成具有优化速度的掩模和集成电路，并在短的设计周期内优化电路面积。
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公开(公告)号：US5984510A
公开(公告)日：1999-11-16
申请号：US740720
申请日：1996-11-01
申请人： Mohan Guruswamy , Daniel Wesley Dulitz , Robert L. Maziasz , Srilata Raman , Venkata K. R. Chiluvuri , Andrea Berens
发明人： Mohan Guruswamy , Daniel Wesley Dulitz , Robert L. Maziasz , Srilata Raman , Venkata K. R. Chiluvuri , Andrea Berens
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for automatically synthesizing standard cell layouts(170) given a circuit netlist, a template describing the layout style and a set of process design rules (136) starts by numerating an ordered sequence of physical netlists from the logical netlist(138). Next, a netlist is selected from the ordered sequence of physical netlists (140). Components are placed according to the selected physical netlist (144). The components are routed to implement interconnections specified by the netlist (154). The components are compacted (156). A next netlist is selected from the ordered sequence of physical netlists. The steps of placing, routing and compacting the components are repeated. The layout with the smallest width is selected(166). Finally, ies, contacts and vias are added and notches filled (170) to improve yield and performance of the circuit.
摘要翻译： 给定电路网表的自动合成标准单元布局（170），描述布局样式的模板和一组过程设计规则（136）的方法通过从逻辑网表（138）计算物理网表的有序序列开始。 接下来，从有序序列的物理网表（140）中选择网表。 组件根据所选择的物理网络表放置（144）。 组件被路由以实现由网表指定的互连（154）。 部件被压实（156）。 从有序的物理网表列表中选择一个下一个网表。 重复放置，布线和压实组件的步骤。 选择宽度最小的布局（166）。 最后，添加，接触和通孔并填充凹口（170）以提高电路的产量和性能。
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公开(公告)号：US20130212549A1
公开(公告)日：2013-08-15
申请号：US13529601
申请日：2012-06-21
申请人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
发明人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts.
摘要翻译： 通过对标准单元布局的可路由特性进行优先级来创建标准单元的布局。 可布线性特征被优先化，使得在单元格布局中强调更有可能提高路由效率的特性。 路由特性的优先级可以由一组权重指示，集合中的每个权重指示标准信元布局的对应可路由特性的优先级。 权重可用于计算标准单元的可路由特性的加权和，从而提供有效地比较不同标准单元布局的可布线性的方式。
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公开(公告)号：US5987086A
公开(公告)日：1999-11-16
申请号：US740721
申请日：1996-11-01
申请人： Srilata Raman , Mohankumar Guruswamy , Daniel Wesley Dulitz , Venkata K. R. Chiluvuri , Robert L. Maziasz
发明人： Srilata Raman , Mohankumar Guruswamy , Daniel Wesley Dulitz , Venkata K. R. Chiluvuri , Robert L. Maziasz
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints (1502) and enhancing yield starts with a prerouting step (152) that routes adjacent transistors using diffusion wiring (1506), routes power and ground nets (1508), routes aligned gates (1510), routes all remaining aligned source/drain nets as well as any special nets (1512). Next, all of the remaining nets are routed using an area based router (1408). Nets are order based on time criticality or net topology (1602). A routing grid is assigned for all the layers to be used in routing (1604). An initial coarse routing is performed (1606). Wire groups are assigned to routing layers (1608). Routing is improved and vias are minimized (1610). A determination is then made whether the routing solution is acceptable (1612). If the routintg solution is not acceptable, the routing space is expanded and routing costs and via costs are modifyied to improve the routing solution. Finally, the best routing solution is picked (1414).
摘要翻译： 一种互连晶体管和其他器件的方法，以便在满足性能约束（1502）和提高产量的情况下优化单元布局的面积，并从利用扩散布线（1506）路由相邻晶体管的预路由步骤（152）开始， 和地网（1508），路由对齐门（1510），路由所有剩余的对齐的源/漏网以及任何特殊网（1512）。 接下来，使用基于区域的路由器（1408）路由所有剩余的网络。 网络是基于时间关键性或网络拓扑的顺序（1602）。 为路由中要使用的所有层分配路由网格（1604）。 执行初始粗略路由（1606）。 线组被分配给路由层（1608）。 路由改进，通孔最小化（1610）。 然后确定路由解决方案是否可接受（1612）。 如果routintg解决方案不可接受，路由空间将被扩展，路由成本和通过成本被修改以改进路由解决方案。 最后，选择最佳路由解决方案（1414）。
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公开(公告)号：US09928331B2
公开(公告)日：2018-03-27
申请号：US14561280
申请日：2014-12-05
CPC分类号： G06F17/5072 , G06F17/5063
摘要： A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout.
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公开(公告)号：US20090158229A1
公开(公告)日：2009-06-18
申请号：US11958605
申请日：2007-12-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
摘要翻译： 集成电路布局设计的面积压缩方法包括确定至少第一电路和第二电路构建块的每层的物理范围边界。 确定物理范围边界包括确定第一电路的每个相应层和第二电路构建块（i）使用部分和（ii）自由部分。 所使用的部分对应于各个电路构建块的功能部分，并且自由部分对应于各个电路构建块的非功能部分。 该方法还包括分别相对于第一电路和第二电路构建块的每层的确定的物理范围边界建立包装密钥。 包装键限定了相应的第一电路或第二电路构建块与另一个电路构建块的压实的互锁特性。
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公开(公告)号：US20080092100A1
公开(公告)日：2008-04-17
申请号：US11811407
申请日：2007-06-11
申请人： Robert L. Maziasz , Vladimir P. Rozenfeld , Iouri Smirnov , Sergei V. Somov , Igor G. Topouzov , Lyudmila Zinchenko
发明人： Robert L. Maziasz , Vladimir P. Rozenfeld , Iouri Smirnov , Sergei V. Somov , Igor G. Topouzov , Lyudmila Zinchenko
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one embodiment, each routing is analyzed with attention to the current that passes through each of the routing's segments in order to compute a current distribution that is used to compute a routing quality vector. In another embodiment, multiple placements are generated and the electromigration placement quality vectors are computed for the various placements with the placement with the best electromigration quality vector being selected. In one embodiment, the placement with the best electromigration quality vector is routed the number of times to determine the routing with the lowest (best) electromigration quality value.
摘要翻译： 提供了一种方法，数据处理系统和计算机程序产品，用于多次路由电路布局，导致多个路由。 为每个路由计算电迁移质量值，并选择具有最佳电迁移质量值的路由。 在一个实施例中，分析每个路由，注意通过每个路由段的电流，以便计算用于计算路由质量向量的当前分布。 在另一个实施例中，生成多个布局，并且针对具有选择了最佳电迁移质量向量的位置的各种布局来计算电迁移放置质量向量。 在一个实施例中，具有最佳电迁移质量矢量的布置被路由多次以确定具有最低（最佳）电迁移质量值的路由。
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公开(公告)号：US6075934A
公开(公告)日：2000-06-13
申请号：US848907
申请日：1997-05-01
IPC分类号： G06F17/50 , H01L27/118
CPC分类号： H01L27/11807 , G06F17/5068
摘要： A method for optimizing contact pin placement in an integrated circuit, wherein a netlist containing connectivity information, and placement information for a semiconductor circuit is read. Each net in the circuit is classified (510). Unblocked tracks are identified for each net in the circuit (512). All contact pins associated with nets having a power supply classification are placed according to a power supply location (513). The blockage for each remaining net is updated. Next, all contact pins for nets residing within a defined diffusion are placed (514) The blockage for each remaining net is updated. Next, all contact pins for nets residing in multiple defined diffusion areas are placed (515).
摘要翻译： 一种用于优化集成电路中的接触针布置的方法，其中包含连接信息的网表和半导体电路的放置信息被读取。 电路中的每个网络被分类（510）。 为电路中的每个网络识别未屏蔽的轨道（512）。 与具有电源分类的网络相关联的所有接触针脚根据电源位置（513）放置。 每个剩余网络的阻塞更新。 接下来，放置位于定义的扩散区内的网络的所有接触针脚（514）更新每个剩余网络的阻塞。 接下来，放置位于多个限定扩散区域的网络的所有接触针脚（515）。
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公开(公告)号：US08978004B2
公开(公告)日：2015-03-10
申请号：US13529601
申请日：2012-06-21
申请人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
发明人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts.
摘要翻译： 通过对标准单元布局的可路由特性进行优先级来创建标准单元的布局。 可布线性特征被优先化，使得在单元格布局中强调更有可能提高路由效率的特性。 路由特性的优先级可以由一组权重指示，集合中的每个权重指示标准信元布局的对应可路由特性的优先级。 权重可用于计算标准单元的可路由特性的加权和，从而提供有效地比较不同标准单元布局的可布线性的方式。
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