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1.发明授权Data processor with circuitry for handling pointers associated with a register exchange operation 失效具有用于处理与寄存器交换操作相关联的指针的电路的数据处理器
公开(公告)号：US5727176A
公开(公告)日：1998-03-10
申请号：US611950
申请日：1996-03-06
CPC分类号： G06F9/30032 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , Y10S707/99936
摘要： A data processor includes a plurality of physical registers and a decoder that decodes a stream of instructions into micro-operations which include speculative operations specifying associated logical registers. The data processor further includes a register-alias table having a plurality of addressable entries corresponding to logical registers, specified by the speculative operations. Each entry of the register-alias table contains a register pointer to a corresponding physical register. The processor further includes a retirement register file that maintains register values of non-speculative operations, and a retirement array that maintains a retirement ordering for the retirement register file. Both the register-alias table and retirement array are updated by circuitry that is responsive to a register exchange operation; the circuitry swapping register pointers associated with first and second entries, respectively.
摘要翻译： 数据处理器包括多个物理寄存器和将指令流解码为微操作的解码器，其包括指定关联的逻辑寄存器的推测性操作。 数据处理器还包括一个寄存器别名表，其具有与由推测操作指定的逻辑寄存器对应的多个可寻址条目。 寄存器别名表的每个条目包含一个到相应物理寄存器的寄存器指针。 处理器还包括维护非投机操作的注册值的退休登记文件，以及维持退休登记文件的退休顺序的退休数组。 寄存器别名表和退出数组都由响应于寄存器交换操作的电路来更新; 电路交换与第一和第二条目相关联的寄存器指针。
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2.发明授权
公开(公告)号：US5613132A
公开(公告)日：1997-03-18
申请号：US129678
申请日：1993-09-30
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A Register Alias Table (RAT) for floating point and integer register renaming within a superscalar microprocessor. The RAT provides register renaming of integer and floating point registers and flags to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture (such as the Intel architecture or Power PC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As uops are simultaneously presented to the RAT logic, their logical sources (both floating point and integer) are used as indices into a RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical source is found. The ROB is composed of many multiple-bit physical registers. During the same clock cycle, the RAT array is updated with new physical destinations granted by an Allocator such that uops in future cycles can read them for their physical sources. Logic is provided for performing prioritized table reads in parallel for all uops and prioritized table writes in parallel for all ups. There is a separate integer and floating point RAT. Up to four uops may be processed by the RAT logic within a given clock cycle.
摘要翻译： 用于在超标量微处理器内进行浮点和整数寄存器重命名的寄存器别名表（RAT）。 RAT提供整数和浮点寄存器和标志的寄存器重命名，以利用比给定宏架构（如Intel架构或Power PC或Alpha设计）中通常可用的更大的物理寄存器集，从而消除虚假的数据依赖 这降低了整体超标量处理性能。 当uops同时呈现给RAT逻辑时，它们的逻辑源（浮点和整数）被用作RAT阵列的索引，以查找驻留在重新排序缓冲器（ROB）中的相应物理寄存器，其中数据为 找到这些逻辑源。 ROB由许多多位物理寄存器组成。 在相同的时钟周期期间，RAT阵列由分配器授予的新的物理目的地进行更新，使得在未来的周期中的uops可以读取它们的物理源。 提供逻辑用于对于所有的并行执行所有的uop并行执行优先级表读取并且对于所有的并行执行优先级表的写入。 有一个单独的整数和浮点RAT。 在给定的时钟周期内，最多可以由RAT逻辑处理四个Uops。
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3.发明授权Floating point register alias table FXCH and retirement floating point register array 失效浮点寄存器别名表FXCH和退出浮点寄存器数组
公开(公告)号：US5499352A
公开(公告)日：1996-03-12
申请号：US129687
申请日：1993-09-30
CPC分类号： G06F9/30032 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , Y10S707/99936
摘要： A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found. An efficient FXCH operation is implemented within the floating point RAT mechanism by switching 6-bit physical register pointers rather than switching the actual data for each physical register which is 86-bits wide. There is a retirement floating point RAT array with dual valid bits and a dual TOS pointer to account for speculative FXCH operations in addition to another floating point RAT array. The retirement floating point RAT array is updated only upon uop retirement whereas the floating point RAT array is updated at uop issuance.
摘要翻译： 一个注册别名表（RAT），包括一个退休浮点RAT阵列，用于在能够进行推测执行的超标量微处理器中重新命名的浮点寄存器。 RAT提供寄存器重命名浮点寄存器，以利用比给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）中通常可用的更大的物理寄存器集，从而消除虚假数据依赖性，从而减少整体 超标量加工性能。 当将一组uops呈现给浮点RAT逻辑时，它们的逻辑源用作浮点RAT阵列的索引，以查找驻留在重新排序缓冲器（ROB）内的对应物理寄存器，其中这些数据为 发现逻辑来源。 通过切换6位物理寄存器指针，而不是切换86位宽的每个物理寄存器的实际数据，在浮点RAT机制内实现高效的FXCH操作。 存在具有双有效位的退休浮点RAT阵列和双TOS指针，以考虑另外的浮点RAT阵列之外的推测性FXCH操作。 退休浮点RAT阵列仅在Uop退出时更新，而浮点RAT阵列在uop发行时被更新。
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公开(公告)号：US5471633A
公开(公告)日：1995-11-28
申请号：US205842
申请日：1994-03-01
CPC分类号： G06F9/3824 , G06F9/30112 , G06F9/3826 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the "missing" portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.
摘要翻译： 描述了具有用于覆盖部分宽度条件失速的习惯识别机制的寄存器别名表单元（RAT）。 当重新命名的逻辑源寄存器大于重命名表指向的相应物理源寄存器时，在RAT重命名过程期间发生部分宽度失速状况。 成语识别器检测uops，使其逻辑目标寄存器为零，并相应地设置和清除iRAT阵列中的零位。 零位指示条目的物理源寄存器的哪些部分已知为零。 当导致部分宽度失速的物理源寄存器的零位指示物理源寄存器的“丢失”部分包含零时，部分宽度失速覆盖机制将覆盖部分宽度失速条件。 通过习惯识别器实现这种RAT重命名机构的微处理器的性能得到改善，因为避免了普通的部分宽度档位。
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5.发明授权Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer 有权具有寄存器存储承诺/推测数据的处理器和具有退出指针的RAT状态历史恢复机制公开(公告)号：US06633970B1
公开(公告)日：2003-10-14
申请号：US09472840
申请日：1999-12-28
申请人： David W. Clift , Darrell D. Boggs , David J. Sager
发明人： David W. Clift , Darrell D. Boggs , David J. Sager
IPC分类号： G06F938
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863
摘要： A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e.g., from a mispredicted branch or other event). The mechanism includes a plurality of physical registers, each physical register can store either architectural data or speculative data. The apparatus also includes a primary array to store a mapping from logical registers to physical registers, the primary array storing a speculative state of the processor. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data. According to another embodiment, a history buffer is coupled to the secondary array and stores historical physical register to logical register mappings performed for each of a plurality of instructions part of a predicted path. The secondary array is movable to a particular speculative state based on the mappings stored in the history buffer, such as to a location where a path failure may occur. The secondary array can then be copied to the primary array when a failure is detected in a predicted path of instructions near where the secondary array is located to allow the processor to recover from the predicted path failure.
摘要翻译： 提供了一种机制，用于允许处理器从预测的指令路径（例如，来自错误预测的分支或其他事件）的故障中恢复。 该机制包括多个物理寄存器，每个物理寄存器可以存储架构数据或推测数据。 该装置还包括主阵列以存储从逻辑寄存器到物理寄存器的映射，主阵列存储处理器的推测状态。 该装置还包括耦合到主阵列的缓冲器，用于存储识别哪些物理寄存器存储架构数据的信息以及哪些物理寄存器存储推测数据。 根据另一个实施例，历史缓冲器耦合到次级阵列，并且将历史物理寄存器存储到针对预测路径的多个指令的每一个执行的逻辑寄存器映射。 基于存储在历史缓冲器中的映射，例如可能发生路径故障的位置，辅助阵列可移动到特定的推测状态。 然后当辅助阵列所在的指令的预测路径中检测到故障时，辅助阵列可以被复制到主阵列，以允许处理器从预测的路径故障恢复。
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