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1.发明授权Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer 有权具有寄存器存储承诺/推测数据的处理器和具有退出指针的RAT状态历史恢复机制公开(公告)号：US06633970B1
公开(公告)日：2003-10-14
申请号：US09472840
申请日：1999-12-28
申请人： David W. Clift , Darrell D. Boggs , David J. Sager
发明人： David W. Clift , Darrell D. Boggs , David J. Sager
IPC分类号： G06F938
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863
摘要： A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e.g., from a mispredicted branch or other event). The mechanism includes a plurality of physical registers, each physical register can store either architectural data or speculative data. The apparatus also includes a primary array to store a mapping from logical registers to physical registers, the primary array storing a speculative state of the processor. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data. According to another embodiment, a history buffer is coupled to the secondary array and stores historical physical register to logical register mappings performed for each of a plurality of instructions part of a predicted path. The secondary array is movable to a particular speculative state based on the mappings stored in the history buffer, such as to a location where a path failure may occur. The secondary array can then be copied to the primary array when a failure is detected in a predicted path of instructions near where the secondary array is located to allow the processor to recover from the predicted path failure.
摘要翻译： 提供了一种机制，用于允许处理器从预测的指令路径（例如，来自错误预测的分支或其他事件）的故障中恢复。 该机制包括多个物理寄存器，每个物理寄存器可以存储架构数据或推测数据。 该装置还包括主阵列以存储从逻辑寄存器到物理寄存器的映射，主阵列存储处理器的推测状态。 该装置还包括耦合到主阵列的缓冲器，用于存储识别哪些物理寄存器存储架构数据的信息以及哪些物理寄存器存储推测数据。 根据另一个实施例，历史缓冲器耦合到次级阵列，并且将历史物理寄存器存储到针对预测路径的多个指令的每一个执行的逻辑寄存器映射。 基于存储在历史缓冲器中的映射，例如可能发生路径故障的位置，辅助阵列可移动到特定的推测状态。 然后当辅助阵列所在的指令的预测路径中检测到故障时，辅助阵列可以被复制到主阵列，以允许处理器从预测的路径故障恢复。
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公开(公告)号：US07219349B2
公开(公告)日：2007-05-15
申请号：US10792154
申请日：2004-03-02
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译： 提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。 重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。 在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。 通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。
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3.发明授权Breaking replay dependency loops in a processor using a rescheduled replay queue 失效使用重新安排的重播队列在处理器中重新播放依赖循环公开(公告)号：US06981129B1
公开(公告)日：2005-12-27
申请号：US09705668
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译： 使用重新安排的重播队列在处理器中重新播放依赖循环。 所述处理器包括用于接收多个指令的重放队列，以及执行所述多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。 当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。 检查器耦合到执行单元以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。
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4.发明授权Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter 失效使用重放队列和计数器在处理器中重新安排多个微操作的方法和装置公开(公告)号：US06877086B1
公开(公告)日：2005-04-05
申请号：US09705678
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译： 使用重放队列在处理器中重新安排多个微操作。 处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地安排执行指令并将每个指令分派到执行单元。 检查器耦合到执行单元以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。
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公开(公告)号：US06385715B1
公开(公告)日：2002-05-07
申请号：US09848423
申请日：2001-05-04
IPC分类号： G06F1500
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译： 提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。 重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。 在一个实施例中，线程特定的重放队列部分可以各自用于存储每个线程的长延时指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。 通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。
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公开(公告)号：US6163838A
公开(公告)日：2000-12-19
申请号：US106857
申请日：1998-06-30
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A computer processor includes a multiplexer having a first input, a second input, and an output, and a scheduler coupled to the multiplexer first input. The processor further includes an execution unit coupled to the multiplexer output. The execution unit is adapted to receive a plurality of instructions from the multiplexer. The processor further includes a replay system coupled to the second multiplexer input and the scheduler. The replay system replays an instruction that has not correctly executed by sending a stop scheduler signal to the scheduler and sending the instruction to the multiplexer.
摘要翻译： 计算机处理器包括具有第一输入，第二输入和输出的多路复用器以及耦合到多路复用器第一输入的调度器。 处理器还包括耦合到多路复用器输出的执行单元。 执行单元适于从多路复用器接收多个指令。 处理器还包括耦合到第二多路复用器输入和调度器的重播系统。 重播系统通过向调度器发送停止调度器信号并将指令发送到多路复用器来重放未正确执行的指令。
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7.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US08850165B2
公开(公告)日：2014-09-30
申请号：US13155055
申请日：2011-06-07
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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8.发明申请Method and Apparatus for Assigning Thread Priority in a Processor or the Like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US20110239221A1
公开(公告)日：2011-09-29
申请号：US13155055
申请日：2011-06-07
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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9.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权在处理器等中分配线程优先级的方法和装置公开(公告)号：US07987346B2
公开(公告)日：2011-07-26
申请号：US13011711
申请日：2011-01-21
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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公开(公告)号：US07877583B2
公开(公告)日：2011-01-25
申请号：US12267394
申请日：2008-11-07
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
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