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    Multifunction Furniture
    2.
    发明申请
    Multifunction Furniture 审中-公开
    多功能家具

    公开(公告)号：US20080250985A1

    公开(公告)日：2008-10-16

    申请号：US12049260

    申请日：2008-03-14

    Applicant: David W. Hall

    Inventor： David W. Hall

    IPC: A47B37/00

    CPC classification number: A47B21/007 ,  A47B81/06 ,  A47C7/72

    Abstract: A furniture frame that incorporates electronic parts into the furniture where the furniture includes an electronic display and an articulated arm and where the articulated arm unit bridges between the frame and an electronic display and it is extendable from and retractable into the frame.

    Abstract translation: 一种家具框架，其将电子部件结合到家具中，其中家具包括电子显示器和铰接臂，并且铰接臂单元在框架和电子显示器之间桥接，并且其可伸缩并进入框架。

    VTOL aerial vehicle
    3.
    发明授权
    VTOL aerial vehicle 有权
    垂直起降飞机

    公开(公告)号：US08220737B2

    公开(公告)日：2012-07-17

    申请号：US12480312

    申请日：2009-06-08

    Applicant: Ryan S. Wood ,  Darold B. Cummings ,  David W. Hall

    Inventor： Ryan S. Wood ,  Darold B. Cummings ,  David W. Hall

    IPC: B64C29/00 ,  B64C15/02 ,  B64C15/14 ,  B64C23/06 ,  B64C3/58 ,  B64C39/06

    CPC classification number: B64C29/0025 ,  B64C39/024 ,  B64C39/068 ,  B64C2201/021 ,  B64C2201/088 ,  B64C2201/162

    Abstract: An aircraft capable of vertical take-off and landing is provided. The aircraft includes a fuselage having a forward portion and an aft portion. A lift fan extends though a duct, which extends through the fuselage. The aircraft further includes a pair of wing sets where each set of wings include first and second wings. Each set of wings has a first wing with a first wing root interconnected to the fuselage forward of a central axis of the lift fan and a second wing having a second wing root interconnected to the fuselage aft of the central axis of the lift fan. The tips of each set of wings are connected. The aircraft further includes a pusher fan.

    Abstract translation: 提供能够垂直起飞和着陆的飞机。 飞机包括具有前部和后部的机身。 升降风扇延伸穿过机身延伸的导管。 飞机还包括一对翼组，其中每组翼包括第一和第二翼。 每组翼具有第一翼，其具有与提升风扇的中心轴线前方的机身相互连接的第一翼根，第二翼具有与提升风扇的中心轴线的机身后部相互连接的第二翼根。 每组翅膀的尖端连接。 飞机还包括推动风扇。

    Fiber optic system including digital controller for fiber optic tunable filter and associated methods
    5.
    发明授权
    Fiber optic system including digital controller for fiber optic tunable filter and associated methods 有权
    光纤系统包括光纤可调滤波器的数字控制器及相关方法

    公开(公告)号：US06559943B1

    公开(公告)日：2003-05-06

    申请号：US09736982

    申请日：2000-12-14

    Applicant: David W. Hall ,  Hitesh R. Mehta

    Inventor： David W. Hall ,  Hitesh R. Mehta

    IPC: G01B1100

    CPC classification number: H04B10/675

    Abstract: A fiber optic system includes an optical fiber carrying an optical signal having a wavelength peak, an optical detector coupled to the optical fiber for detecting a current optical level (e.g. a photon power level), and a tunable optical filter coupled to the optical fiber upstream from the optical detector. The system further includes a controller connected to the optical detector and the tunable optical filter, for stepping the tunable optical filter over a sequence of wavelengths while analyzing respective optical levels, and for reversing the stepping direction of the tunable optical filter, based upon the current optical level being less than a prior optical level, to locate the wavelength peak of the at least one optical signal. A sample rate is reduced when the wavelength peak of the optical signal is located, to thereby reduce a power consumption of the controller.

    Abstract translation: 光纤系统包括承载具有波长峰值的光信号的光纤，耦合到光纤的光学检测器，用于检测当前光学电平（例如，光子功率电平）以及耦合到上游光纤的可调光滤波器 从光学检测器。 该系统还包括连接到光学检测器和可调谐滤光器的控制器，用于在分析各个光学水平的同时对可调谐光学滤波器进行步进，同时基于电流来反转可调谐滤光器的步进方向 光学水平小于先前光学水平，以定位至少一个光信号的波长峰值。 当光信号的波长峰值位于时，采样率降低，从而降低控制器的功耗。

    Method for converting an integrated circuit design for an upgraded process
    6.
    发明授权
    Method for converting an integrated circuit design for an upgraded process 失效
    用于转换升级过程的集成电路设计的方法

    公开(公告)号：US5936868A

    公开(公告)日：1999-08-10

    申请号：US812805

    申请日：1997-03-06

    Applicant: David W. Hall

    Inventor： David W. Hall

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method for converting an original integrated circuit (IC) design to an updated IC design for an updated manufacturing process includes accessing a mask database for the original IC design and manipulating the data by various scaling steps and other modifications. The original IC design may include contacts so the method includes the steps of performing a first downward size scaling on the mask data to scale down the original IC design, and selectively performing a second downward size scaling on the mask data to further scale down the contacts. The step of selectively performing the second downward size scaling may preferably include the steps of displaying and viewing an image of the IC design to aid in selection. The vias of the IC design may also be scaled downward. The method may also further include the step of selectively performing a downward size scaling on the mask data in at least one dimension to further scale down a size of the polysilicon gates. The method may further include the steps of selectively performing an upward size scaling on the mask data to scale up the power supply rails, and selectively performing an upward size scaling on the mask data to scale up the bond pads. The original test and alignment structures are preferably replaced by new test structures and alignment keys for the updated process, and new ESD protection may be substituted for the original ESD protection.

    Abstract translation: 用于将原始集成电路（IC）设计转换为用于更新的制造过程的更新的IC设计的方法包括访问用于原始IC设计的掩模数据库并且通过各种缩放步骤和其他修改来操纵数据。 原始IC设计可以包括联系人，因此该方法包括以下步骤：对掩模数据执行第一向下尺寸缩放以缩小原始IC设计，并且选择性地对掩码数据执行第二向下尺寸缩放以进一步缩小触点 。 选择性地执行第二向下尺寸缩放的步骤可以优选地包括显示和查看IC设计的图像以辅助选择的步骤。 IC设计的通孔也可以向下扩展。 该方法还可以包括在至少一个维度上选择性地对掩模数据执行向下尺寸缩放以进一步缩小多晶硅栅极的尺寸的步骤。 该方法还可以包括以下步骤：选择性地对掩模数据执行向上尺寸缩放以放大电源轨，并且选择性地对掩模数据执行向上尺寸缩放以放大接合焊盘。 原始的测试和对准结构优选地被新的测试结构和用于更新过程的对准键替代，并且新的ESD保护可以代替原始的ESD保护。

    Secure wireless LAN device including tamper resistant feature and associated method
    8.
    发明授权
    Secure wireless LAN device including tamper resistant feature and associated method 有权
    安全无线局域网设备，包括防篡改功能和相关方法

    公开(公告)号：US07441126B2

    公开(公告)日：2008-10-21

    申请号：US09761173

    申请日：2001-01-16

    Applicant: Russell Dellmo ,  James Bergman ,  David W. Hall

    Inventor： Russell Dellmo ,  James Bergman ,  David W. Hall

    IPC: G06F21/00

    CPC classification number: H04L63/1441 ,  G06F21/602 ,  G06F21/606 ,  G06F21/72 ,  G06F21/86 ,  H04W12/02 ,  H04W12/12 ,  H04W84/12 ,  H04W88/02

    Abstract: A secure wireless LAN device includes a housing, a wireless transceiver carried by the housing, and a cryptography circuit carried by the housing. The cryptography circuit may operate using cryptography information and may also render unuseable the cryptography information based upon tampering. The cryptography circuit may include at least one volatile memory for storing the cryptography information, and a battery for maintaining the cryptography information in the at least one volatile memory. Accordingly, the cryptography circuit may further include at least one switch operatively connected to the housing for disconnecting the battery from the at least one volatile memory so that the cryptography information therein is lost based upon breach of the housing. The cryptographic information may comprise a cryptography key and/or at least a portion of a cryptography algorithm. This cryptographic information remains relatively secure and is lost upon tampering, such as removing the housing.

    Abstract translation: 安全无线LAN设备包括外壳，由外壳承载的无线收发器以及由外壳承载的加密电路。 加密电路可以使用加密信息进行操作，并且还可以基于篡改而使密码学信息不可用。 密码学电路可以包括用于存储加密信息的至少一个易失性存储器，以及用于在至少一个易失性存储器中维护密码信息的电池。 因此，密码学电路还可以包括至少一个可操作地连接到壳体的开关，用于将电池与所述至少一个易失性存储器断开连接，使得其中的密码信息基于违反外壳而丢失。 加密信息可以包括加密密钥和/或加密算法的至少一部分。 这种加密信息保持相对安全，并且在篡改时丢失，例如移除外壳。

    Low noise logic family
    10.
    发明授权
    Low noise logic family 失效
    低噪声逻辑系列

    公开(公告)号：US5514982A

    公开(公告)日：1996-05-07

    申请号：US292482

    申请日：1994-08-18

    Applicant: David W. Hall ,  J. G. Dooley ,  Arecio A. Hernandez

    Inventor： David W. Hall ,  J. G. Dooley ,  Arecio A. Hernandez

    IPC: H03K19/003 ,  H03K19/0944 ,  H03L7/099 ,  H03L7/16 ,  H03K19/08

    CPC classification number: H03L7/0995 ,  H03K19/00361 ,  H03K19/09441 ,  H03L7/16

    Abstract: A low noise logic (LNL) family is disclosed. An inverter 10 has a pair of load devices NL1, NL2 coupled to the drains of NMOS transistors N 1, N2. The input signal is coupled to the gate of N 1. The drain of N 1 is coupled to the gate of N2. A constant current source 12 is coupled between V.sub.ss and the sources of the transistors N1,N2. Trickle current devices NTR1, NTR2 are coupled to the drains of N 1, N2, respectively to insure input control of the output states. A high logic signal on the gate of N1 steers the constant current to the load NL1 and turns NL2 off. A low logic signal on the gate of N1 turns N1 off and applies a high voltage to the gate of N2, turning N2 on. N2 steers the constant current to NL2.

    Abstract translation: 公开了一种低噪声逻辑（LNL）系列。 反相器10具有耦合到NMOS晶体管N1，N2的漏极的一对负载装置NL1，NL2。 输入信号耦合到N 1的栅极.N 1的漏极耦合到N2的栅极。 恒流源12耦合在Vss和晶体管N1，N2的源极之间。 涓流电流装置NTR1，NTR2分别耦合到N 1，N 2的漏极，以确保输出状态的输入控制。 N1的门上的高逻辑信号转向负载NL1的恒定电流并使NL2关断。 N1的栅极上的低逻辑信号将N1关断，并向N2的栅极施加高电压，打开N2。 N2将恒流转向NL2。

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