公开(公告)号：US08750324B2

公开(公告)日：2014-06-10

申请号：US12557736

申请日：2009-09-11

Applicant: David W. Hansquine ,  Brett C. Walker ,  Muhammad Asim Muneer

Inventor： David W. Hansquine ,  Brett C. Walker ,  Muhammad Asim Muneer

IPC: H04L12/66

CPC classification number: H04L12/40013 ,  H04L12/403

Abstract: Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.

Abstract translation: 本文公开的实施例解决了对单个有线总线接口的需要。 在一个方面，一种设备通过单线总线与第二设备通信，该驱动器用于使用包括起始符号，写指示符符号，地址和数据符号的写入帧来驱动总线。 在另一方面，设备在读取帧期间在单线总线上接收一个或多个数据符号。 在另一方面，一种设备通过单线总线与第二设备通信，该接收机用于在单线总线上接收包括开始符号，写指示符符号，地址和一个或多个数据符号的帧，以及 当写入指示符识别写入帧时，驱动器用于驱动与地址相关联的读取数据。 还提出了各种其他方面。 这些方面提供了在单个有线总线上的通信，其允许减少引脚，焊盘或设备之间的块间连接。

公开(公告)号：US20080215944A1

公开(公告)日：2008-09-04

申请号：US12122702

申请日：2008-05-18

Applicant: Roberto Fabian Averbuj ,  David W. Hansquine

Inventor： Roberto Fabian Averbuj ,  David W. Hansquine

IPC: G01R31/28

CPC classification number: G11C29/16

Abstract: Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

Abstract translation: 公开了具有分布式解释和广义命令协议的内置自检（BIST）架构。 在一个实施例中，公开了一种系统，并且包括被配置为存储算法以测试多个存储器模块的集中式内置自检（BIST）控制器。 BIST控制器将算法存储为符合命令协议的一组通用命令。 BIST控制器配置为将一组通用命令发送到定序器。

公开(公告)号：US08661274B2

公开(公告)日：2014-02-25

申请号：US12701657

申请日：2010-02-08

Applicant: David W. Hansquine ,  Richard Gerard Hofmann ,  Richard Alan Moore

Inventor： David W. Hansquine ,  Richard Gerard Hofmann ,  Richard Alan Moore

IPC: G06F1/04 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.

Abstract translation: 自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化条件自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。 在一个实施例中，AVS包括数据库。 数据库可以配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。 数据库允许快速的电压电平决定。 在一个实施例中，电压偏移被添加到从数据库检索的电压电平，该电压电平对应于功能电路的目标工作频率。 在另一个实施例中，从对应于功能电路的目标工作频率和温度水平的数据库检索电压电平。 AVS可以由参考数据库的基于软件的模块部分或完全控制，以进行电压电平决定。

公开(公告)号：US07814380B2

公开(公告)日：2010-10-12

申请号：US12122702

申请日：2008-05-18

Applicant: Roberto Fabian Averbuj ,  David W. Hansquine

Inventor： Roberto Fabian Averbuj ,  David W. Hansquine

IPC: G11C29/00

CPC classification number: G11C29/16

Abstract: Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

Abstract translation: 公开了具有分布式解释和广义命令协议的内置自检（BIST）架构。 在一个实施例中，公开了一种系统，并且包括被配置为存储算法以测试多个存储器模块的集中式内置自检（BIST）控制器。 BIST控制器将算法存储为符合命令协议的一组通用命令。 BIST控制器配置为将一组通用命令发送到定序器。

公开(公告)号：US20110004774A1

公开(公告)日：2011-01-06

申请号：US12701657

申请日：2010-02-08

Applicant: David W. Hansquine ,  Richard Gerard Hofmann ,  Richard Alan Moore

Inventor： David W. Hansquine ,  Richard Gerard Hofmann ,  Richard Alan Moore

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.

Abstract translation: 自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化条件自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。 在一个实施例中，AVS包括数据库。 数据库可以配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。 数据库允许快速的电压电平决定。 在一个实施例中，电压偏移被添加到从数据库检索的电压电平，该电压电平对应于功能电路的目标工作频率。 在另一个实施例中，从对应于功能电路的目标工作频率和温度水平的数据库检索电压电平。 AVS可以由参考数据库的基于软件的模块部分或完全控制，以进行电压电平决定。

公开(公告)号：US20100064074A1

公开(公告)日：2010-03-11

申请号：US12557736

申请日：2009-09-11

Applicant: David W. Hansquine ,  Brett C. Walker ,  Muhammad Asim Muneer

Inventor： David W. Hansquine ,  Brett C. Walker ,  Muhammad Asim Muneer

IPC: G06F1/12 ,  G06F13/00

CPC classification number: H04L12/40013 ,  H04L12/403

Abstract: Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.

Abstract translation: 本文公开的实施例解决了对单个有线总线接口的需要。 在一个方面，一种设备通过单线总线与第二设备通信，该驱动器用于使用包括起始符号，写指示符符号，地址和数据符号的写入帧来驱动总线。 在另一方面，设备在读取帧期间在单线总线上接收一个或多个数据符号。 在另一方面，一种设备通过单线总线与第二设备通信，该接收机用于在单线总线上接收包括开始符号，写指示符符号，地址和一个或多个数据符号的帧，以及 当写入指示符识别写入帧时，驱动器用于驱动与地址相关联的读取数据。 还提出了各种其他方面。 这些方面提供了在单个有线总线上的通信，其允许减少引脚，焊盘或设备之间的块间连接。

公开(公告)号：US07392442B2

公开(公告)日：2008-06-24

申请号：US10630480

申请日：2003-07-29

Applicant: Roberto Fabian Averbuj ,  David W. Hansquine

Inventor： Roberto Fabian Averbuj ,  David W. Hansquine

IPC: G11C29/00

CPC classification number: G11C29/16

Abstract: A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

Abstract translation: 描述了具有分布式算法解释的内置自检（BIST）架构。 该架构包括三层抽象层次：集中式BIST控制器，一组排序器和一组存储器接口。 BIST控制器存储一组命令，通常定义用于测试存储器模块的算法，而不考虑存储器模块的物理特性或时序要求。 顺控程序根据命令协议解释命令并生成序列的存储器操作。 存储器接口根据存储器模块的物理特性将存储器操作应用于存储器模块，例如通过基于存储器模块的行列排列来转换地址和数据信号，以实现由命令描述的位模式。 命令协议允许以非常简洁的方式描述强大的算法，其可以应用于具有不同特征的存储器模块。

公开(公告)号：US07184915B2

公开(公告)日：2007-02-27

申请号：US10630516

申请日：2003-07-29

Applicant: David W. Hansquine ,  Roberto F. Averbuj

Inventor： David W. Hansquine ,  Roberto F. Averbuj

IPC: G01R31/00

CPC classification number: G11C29/16

Abstract: A distributed, hierarchical built-in self-test (BIST) architecture for testing the operation of one or more memory modules is described. As described, the architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces coupled to memory modules. The BIST controller stores a set of commands that generically define an algorithm for testing the memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers receive the commands and generate sequences of memory operations in accordance with the timing requirements of the various memory modules. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands.

Abstract translation: 描述了用于测试一个或多个存储器模块的操作的分布式分层内置自检（BIST）架构。 如上所述，架构包括三层抽象层：集中式BIST控制器，一组排序器以及一组耦合到存储器模块的存储器接口。 BIST控制器存储一组命令，通常定义用于测试存储器模块的算法，而不考虑存储器模块的物理特性或时序要求。 定序器根据各种存储器模块的时序要求接收命令并产生存储器操作序列。 存储器接口根据存储器模块的物理特性将存储器操作应用于存储器模块，例如通过基于存储器模块的行列排列来转换地址和数据信号，以实现由命令描述的位模式。

公开(公告)号：US06757864B1

公开(公告)日：2004-06-29

申请号：US09544324

申请日：2000-04-06

Applicant: David W. Hansquine

Inventor： David W. Hansquine

IPC: H03M1300

CPC classification number: H03M13/4107

Abstract: The present invention discloses a method and apparatus for efficiently reading and storing state metrics in memory to enhance high-speed ACS Viterbi decoder implementations. The method includes applying an addressing scheme that determines the address locations of source state metrics during a process cycle. The source state metrics are then read from the address locations during the process cycle and applied to an add-compare-select butterfly operation of a Viterbi algorithm implementation to generate target state metrics. The method then stores each of the target state metrics into the address locations previously occupied by the source state metrics. The method further provides an addressing scheme that determines the address locations of the source state metrics based on a process cycle counter that is incremented and rotated in accordance with the process cycle. The method also provides an addressing scheme that employs a predetermined function to determine the address locations of the source state metrics.

Abstract translation: 本发明公开了一种用于在存储器中高效地读取和存储状态度量以增强高速ACS维特比解码器实现的方法和装置。 该方法包括应用在处理周期期间确定源状态度量的地址位置的寻址方案。 然后在处理周期期间从地址位置读取源状态度量，并将其应用于维特比算法实现的加法比选择蝶形运算以产生目标状态度量。 该方法然后将每个目标状态度量存储在先前由源状态度量占据的地址位置中。 该方法还提供了一种寻址方案，其基于根据处理周期递增和旋转的处理周期计数器来确定源状态度量的地址位置。 该方法还提供了采用预定函数来确定源状态度量的地址位置的寻址方案。