公开(公告)号：US20110180693A1

公开(公告)日：2011-07-28

申请号：US13013199

申请日：2011-01-25

申请人： David W. Ritter ,  Philip Golden ,  Aaron Gibby ,  Carl Warren Craddock

发明人： David W. Ritter ,  Philip Golden ,  Aaron Gibby ,  Carl Warren Craddock

IPC分类号： H01J40/14

CPC分类号： G01N21/55 ,  G01J1/46 ,  G01J9/00 ,  G01S17/08 ,  H01L31/101

摘要： An area effective system and method for improving power supply rejection ratio (PSRR) in an optical sensor front end, is provided. Moreover, low pass filter (LPF) that enables the reference voltage in the front end of the optical sensor, to be referred to the same substrate as that employed by the sensor. In one example, the LPF includes a capacitor, implemented using a Deep-N-Well (DNW) depletion capacitor, which is utilized to connect the reference voltage to the same substrate. Additionally, the DNW allows an area efficient realization of the LPF. The system and method disclosed herein improves the PSRR by a factor of around 40 dB for 5 MHz modulation.

摘要翻译： 提供了一种用于改善光学传感器前端中的电源抑制比（PSRR）的区域有效系统和方法。 此外，使得能够将光学传感器前端的参考电压的低通滤波器（LPF）称为与传感器采用的相同的衬底。 在一个示例中，LPF包括使用深N阱（DNW）耗尽电容器实现的电容器，其用于将参考电压连接到相同的衬底。 此外，DNW允许区域高效地实现LPF。 本文所公开的系统和方法将对于5MHz调制的PSRR提高约40dB的系数。

公开(公告)号：US20110115047A1

公开(公告)日：2011-05-19

申请号：US12794236

申请日：2010-06-04

申请人： Francois Hebert ,  Aaron Gibby ,  Stephen Joseph Gaul

发明人： Francois Hebert ,  Aaron Gibby ,  Stephen Joseph Gaul

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/331 ,  H01L29/73 ,  H01L21/306

CPC分类号： H01L21/743 ,  H01L21/76229 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8249 ,  H01L27/0733 ,  H01L28/90 ,  H01L29/66272

摘要： Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.

摘要翻译： 半导体器件的方法和结构可以使用不同宽度的掩模开口来形成不同深度，不同材料和不同功能的结构。 例如，描述了用于形成浅沟槽隔离，深隔离，沟槽电容器，基极，发射极和集电极以及横向双极晶体管的其它结构的工艺和结构。

公开(公告)号：US20110084318A1

公开(公告)日：2011-04-14

申请号：US12726855

申请日：2010-03-18

申请人： Aaron Gibby

发明人： Aaron Gibby

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L29/1066 ,  H01L29/66901

摘要： A junction field effect transistor semiconductor device and method can include a top gate interposed between a source region and a drain region, and which can extend across an entire surface of the channel region from the source region to the drain region. Top gate doping can be configured such that the top gate can remain depleted throughout operation of the device. An embodiment of a device so configured can be used in precision, high-voltage applications.

摘要翻译： 结型场效应晶体管半导体器件和方法可以包括插入在源极区域和漏极区域之间的顶栅极，并且其可以在从源极区域到漏极区域的沟道区域的整个表面上延伸。 顶栅掺杂可以被配置为使得顶栅可以在器件的整个操作期间保持耗尽。 这样配置的装置的实施例可以用于精密，高电压应用中。