公开(公告)号：US07362355B1

公开(公告)日：2008-04-22

申请号：US10634339

申请日：2003-08-04

申请人： David Xiao Dong Yang ,  Michael Frank ,  Odutola Oluseye Ewedemi ,  William R. Bidermann ,  Ricardo J. Motta ,  Justin Reyneri ,  Hui Tian

发明人： David Xiao Dong Yang ,  Michael Frank ,  Odutola Oluseye Ewedemi ,  William R. Bidermann ,  Ricardo J. Motta ,  Justin Reyneri ,  Hui Tian

IPC分类号： H04N5/235

CPC分类号： H04N5/378 ,  H04N5/3575 ,  H04N5/361 ,  H04N5/367

摘要： A system-on-chip imaging system includes an image sensor of a two-dimensional array of pixel elements providing pixel data representing an image of a scene, a data memory for storing pixel codewords whereby at least some of the pixel codewords are indicative of the pixel data, a programmable lookup table for providing LUT codewords as output data, and a processing unit for receiving LUT codewords from the lookup table and generating output image data. In operation, a first pixel codeword stored in the data memory is used to index the lookup table for causing the lookup table to provide a respective LUT codeword to the processing unit. The processing unit operates to perform one or more image processing functions in response to the LUT codeword. The lookup table can be programmed to perform a variety of image processing functions, including defective pixel correction, CDS subtraction, privacy masking and dark signal subtraction.

摘要翻译： 片上系统成像系统包括提供表示场景图像的像素数据的二维阵列阵列的图像传感器，用于存储像素码字的数据存储器，其中至少一些像素码字指示 像素数据，用于提供LUT码字作为输出数据的可编程查找表，以及用于从查找表接收LUT码字并产生输出图像数据的处理单元。 在操作中，存储在数据存储器中的第一像素码字用于索引查找表，以使查找表向处理单元提供相应的LUT码字。 处理单元操作以响应于LUT码字执行一个或多个图像处理功能。 可以对查找表进行编程，以执行各种图像处理功能，包括缺陷像素校正，CDS减法，隐私掩蔽和暗信号相减。

公开(公告)号：US07483058B1

公开(公告)日：2009-01-27

申请号：US10634302

申请日：2003-08-04

申请人： Michael Frank ,  Ricardo J. Motta ,  Justin Reyneri ,  David Xiao Dong Yang ,  William R. Bidermann ,  Odutola Oluseye Ewedemi

发明人： Michael Frank ,  Ricardo J. Motta ,  Justin Reyneri ,  David Xiao Dong Yang ,  William R. Bidermann ,  Odutola Oluseye Ewedemi

IPC分类号： H04N5/228

CPC分类号： H04N5/3355 ,  H04N5/232

摘要： A video imaging system includes a digital image sensor for performing image capture operations and a digital image processor for performing image processing operations. The digital image sensor includes a sensor array outputting digital pixel data, an image buffer for storing the pixel data, a first processor and a first interface circuit for transferring the pixel data onto a pixel bus. The digital image processor includes a second interface circuit coupled to receive the pixel data from the pixel bus, a frame buffer coupled to store the pixel data, an image processing pipeline for processing the pixel data stored in the frame buffer into video data, and a second processor. The digital image sensor and the digital image processor transfer control information over a control interface bus and the digital image sensor performs the image capture operations independent of the image processing operations performed by the digital image processor.

摘要翻译： 视频成像系统包括用于执行图像捕获操作的数字图像传感器和用于执行图像处理操作的数字图像处理器。 数字图像传感器包括输出数字像素数据的传感器阵列，用于存储像素数据的图像缓冲器，用于将像素数据传送到像素总线的第一处理器和第一接口电路。 数字图像处理器包括耦合以从像素总线接收像素数据的第二接口电路，耦合以存储像素数据的帧缓冲器，用于将存储在帧缓冲器中的像素数据处理为视频数据的图像处理流水线，以及 第二处理器。 数字图像传感器和数字图像处理器通过控制接口总线和数字图像传感器传送控制信息执行与数字图像处理器执行的图像处理操作无关的图像捕获操作。

公开(公告)号：US06985181B2

公开(公告)日：2006-01-10

申请号：US09755910

申请日：2001-01-03

申请人： Odutola Oluseye Ewedemi ,  Zhonghan John Deng ,  Ricardo Jansson Motta ,  David Xiao Dong Yang

发明人： Odutola Oluseye Ewedemi ,  Zhonghan John Deng ,  Ricardo Jansson Motta ,  David Xiao Dong Yang

IPC分类号： H04N3/14

CPC分类号： H04N1/00307 ,  H04N5/232 ,  H04N5/374 ,  H04N7/142 ,  H04N2201/0068

摘要： An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

摘要翻译： 图像传感器包括传感器或像素阵列，数据存储器和逻辑电路，全部制造在同一集成芯片上。 传感器或像素阵列输出数字信号作为表示场景图像的像素数据。 数据存储器耦合到用于存储像素数据的传感器或像素阵列。 逻辑电路耦合到数据存储器并提供用于导出像素数据的存储器接口。 存储器接口可以是SRAM，DRAM或分组协议同步DRAM接口之一。 在图像传感器中包括存储器接口允许图像传感器直接耦合到外部图像处理单元的存储器接口端口。 图像处理单元可以使用传统的存储器访问协议访问图像传感器，从而提高图像处理单元的效率并降低操作复杂度。

公开(公告)号：US06778212B1

公开(公告)日：2004-08-17

申请号：US09665523

申请日：2000-09-19

申请人： Zhonghan John Deng ,  David Xiao Dong Yang ,  Odutola Oluseye Ewedemi

发明人： Zhonghan John Deng ,  David Xiao Dong Yang ,  Odutola Oluseye Ewedemi

IPC分类号： H04N5228

CPC分类号： H04N5/2355 ,  H04N5/235 ,  H04N5/335

摘要： An image sensor, including a substrate having formed thereon by a CMOS process a digital sensor array having a plurality of digital pixel sensors which output analog signals corresponding to a desired image. The digital sensor array further includes supporting circuitry for converting the analog signals produced by the digital pixel sensors to digital signals corresponding to the desired image. Filter circuitry, for converting the digital signals to digital values representative of the light intensity impinging upon the plurality of digital pixel sensors, is also formed on the substrate using CMOS fabrication processes. Memory devices, including a data memory, a threshold memory, and a time index memory are formed on the substrate using CMOS fabrication techniques. A clock circuit is also formed on the substrate using CMOS fabrication processes. Programmable logic structures are formed on the substrate using CMOS fabrication processes. The programmable logic structure can be configured into a variety of circuitry or routing so as to facilitate customization or specialization of the image sensor.

摘要翻译： 一种图像传感器，包括通过CMOS工艺在其上形成的基板的数字传感器阵列，该数字传感器阵列具有输出对应于期望图像的模拟信号的多个数字像素传感器。 数字传感器阵列还包括用于将由数字像素传感器产生的模拟信号转换成对应于期望图像的数字信号的支持电路。 用于将数字信号转换成表示在多个数字像素传感器上照射的光强度的数字值的滤波器电路也使用CMOS制造工艺形成在衬底上。 使用CMOS制造技术在衬底上形成包括数据存储器，阈值存储器和时间索引存储器的存储器件。 使用CMOS制造工艺也在衬底上形成时钟电路。 使用CMOS制造工艺在衬底上形成可编程逻辑结构。 可编程逻辑结构可以配置成各种电路或路由，以便于图像传感器的定制或专业化。

公开(公告)号：US06765619B1

公开(公告)日：2004-07-20

申请号：US09542196

申请日：2000-04-04

申请人： Zhonghan Deng ,  David Xiao Dong Yang ,  Xi Peng ,  Odutola Oluseye Ewedemi ,  Ricardo Jansson Motta ,  Yi-Hen Wei

发明人： Zhonghan Deng ,  David Xiao Dong Yang ,  Xi Peng ,  Odutola Oluseye Ewedemi ,  Ricardo Jansson Motta ,  Yi-Hen Wei

IPC分类号： H04N5235

CPC分类号： H04N5/2351 ,  H04N5/2353

摘要： A method of optimizing the exposure times of regions of pixels of an image sensor array during exposure is accomplished by utilizing time interval sampling of an image sensor array comprising of pixels configured to generate digital image signals. Luminance values are extracted from each digital image signal and analyzed to determine if a pixel has reached the optimal exposure. If a pixel has reached the optimal exposure, subsequent digital image signals from this pixel will not be recorded. This preserves the recording of the optimal digital image signal generated by the pixel at the time when the pixel reached its optimal exposure. This process of selectively terminating the recording of digital image signals based on optimal exposures of the pixels can be performed on individual pixels or can be performed on a region of pixels.

摘要翻译： 通过利用包括被配置为产生数字图像信号的像素的图像传感器阵列的时间间隔采样来优化曝光期间图像传感器阵列的像素区域的曝光时间的方法。 从每个数字图像信号提取亮度值，并进行分析，以确定像素是否达到最佳曝光。 如果像素达到最佳曝光，则不会记录来自该像素的后续数字图像信号。 这保持了当像素达到其最佳曝光时由像素产生的最佳数字图像信号的记录。 可以基于像素的最佳曝光选择性地终止数字图像信号的记录的处理，或者可以在像素区域上执行。

公开(公告)号：US06831684B1

公开(公告)日：2004-12-14

申请号：US09638503

申请日：2000-08-15

申请人： Odutola Oluseye Ewedemi ,  Zhonghan John Deng ,  Ricardo Jansson Motta ,  David Xiao Dong Yang

发明人： Odutola Oluseye Ewedemi ,  Zhonghan John Deng ,  Ricardo Jansson Motta ,  David Xiao Dong Yang

IPC分类号： H04N5228

CPC分类号： H04N1/00307 ,  H04N5/232 ,  H04N5/235 ,  H04N7/142 ,  H04N2201/0068

摘要： An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

摘要翻译： 图像传感器包括传感器阵列，用于存储像素数据的数据存储器和像素归一化电路。 传感器阵列具有像素元件的二维阵列，并输出数字信号作为表示场景图像的像素数据。 由传感器阵列输出的像素数据以传感器位排列方式排列，并且像素归一化电路将像素数据重排为像素位顺序。 在另一个实施例中，图像传感器包括传感器阵列，数据存储器和像素归一化电路，全部制造在单个集成电路上。 像素归一化电路包括像素重排电路，格雷码二进制转换电路，复位减法电路和多采样归一化电路中的一个或多个。 最后，提供了一个格雷码到二进制转换电路，用于高速转换。

公开(公告)号：US06809666B1

公开(公告)日：2004-10-26

申请号：US09639520

申请日：2000-08-15

申请人： Odutola Oluseye Ewedemi ,  David Xiao Dong Yang ,  Xi Peng

发明人： Odutola Oluseye Ewedemi ,  David Xiao Dong Yang ,  Xi Peng

IPC分类号： H03M704

CPC分类号： H04N1/00307 ,  H04N5/232 ,  H04N5/235 ,  H04N7/142 ,  H04N2201/0068

摘要： An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

摘要翻译： 图像传感器包括传感器阵列，用于存储像素数据的数据存储器和像素归一化电路。 传感器阵列具有像素元件的二维阵列，并输出数字信号作为表示场景图像的像素数据。 由传感器阵列输出的像素数据以传感器位排列方式排列，并且像素归一化电路将像素数据重排为像素位顺序。 在另一个实施例中，图像传感器包括传感器阵列，数据存储器和像素归一化电路，全部制造在单个集成电路上。 像素归一化电路包括像素重排电路，格雷码二进制转换电路，复位减法电路和多采样归一化电路中的一个或多个。 最后，提供了一个格雷码到二进制转换电路，用于高速转换。

公开(公告)号：US06693575B1

公开(公告)日：2004-02-17

申请号：US10150553

申请日：2002-05-17

申请人： David Xiao Dong Yang ,  William R. Bidermann

发明人： David Xiao Dong Yang ,  William R. Bidermann

IPC分类号： H03M112

CPC分类号： H03M1/123 ,  H03M1/56

摘要： A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout. This creates an analog read port for minimum amount of circuitry increase.

摘要翻译： 本文描述了具有减少的信道电路的多通道位串行模数转换器，其中一位比较器电路在位于输入通道内的第一部分和位于输入通道外部的第二部分之间分开。 比较器的外部部分和一位锁存器由多个输入通道共享。 在优选实施例中，在单个集成电路中制造像素元件的二维传感器阵列。 每个像素元件是包括光电检测器和一位比较器的前端部分的输入通道。 比较器的外部部分和一位锁存器形成在传感器阵列的外围，并被一组像素元件共享，诸如像素元件列。 在一个实施例中，通过将反相器的输出连接到比较器的控制信号端，比较器也可以用作模拟读出的缓冲器。 这将创建一个模拟读取端口，以最小化电路数量。

公开(公告)号：US06310571B1

公开(公告)日：2001-10-30

申请号：US09823443

申请日：2001-03-30

申请人： David Xiao Dong Yang ,  William R. Bidermann

发明人： David Xiao Dong Yang ,  William R. Bidermann

IPC分类号： H03M138

CPC分类号： H03M1/123 ,  H03M1/56

摘要： A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

摘要翻译： 电路包括用于在多个模拟输入信号之间进行复用并将所选择的模拟输入信号转换为数字码表示的模拟（A / D）转换器。 A / D转换器包括比较器，其具有被连接以接收具有多个电平的第一信号的第一输入端，被连接以接收多个模拟输入信号的第二输入端，以及用于接收多个数的第三输入端 的输入选择信号。 比较器包括将多个模拟输入信号耦合到多个对应的输入信号路径的多路复用器。 多路复用器根据多个输入选择信号选择多个输入信号路径中的一个。 在一个实施例中，A / D转换器应用于数字图像传感器中，用于使用多通道位串行ADC技术进行像素级模数转换。

公开(公告)号：US06788240B2

公开(公告)日：2004-09-07

申请号：US10618398

申请日：2003-07-11

申请人： Justin Reyneri ,  David Xiao Dong Yang

发明人： Justin Reyneri ,  David Xiao Dong Yang

IPC分类号： H03M136

CPC分类号： H03M1/123 ,  H03M1/34

摘要： A circuit includes an input terminal coupled to receive an analog input signal, a multiple number of sample-and-hold circuits and a multiple number of analog-to-digital (A/D) converters. The input terminal of each of the sample-and-hold circuits is coupled to receive the analog input signal. Each of the A/D converters has an input terminal and an output terminal, where the input terminal is coupled to an output terminal of a corresponding one of the sample-and-hold circuits. In operation, the sample-and-hold circuits sample the analog input signal sequentially and store a multiple number of analog samples at each of the sample-and-hold circuits. The A/D converters convert the analog samples in parallel to generate digital values at the output terminals of each of the A/D converters representative of each of the analog samples. In one embodiment, the A/D converters are implemented based on a multi-channel bit-serial (MCBS) analog-to-digital conversion scheme.

摘要翻译： 电路包括耦合以接收模拟输入信号的输入端，多个采样保持电路和多个模拟（A / D）转换器。 每个采样和保持电路的输入端耦合以接收模拟输入信号。 每个A / D转换器具有输入端和输出端，其中输入端耦合到相应的一个采样和保持电路的输出端。 在运行中，采样和保持电路顺序采样模拟输入信号，并在每个采样保持电路上存储多个模拟采样。 A / D转换器并行转换模拟采样，以在代表每个模拟采样的每个A / D转换器的输出端产生数字值。 在一个实施例中，A / D转换器基于多通道位串行（MCBS）模数转换方案来实现。