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公开(公告)号：US06686785B2
公开(公告)日：2004-02-03
申请号：US09975359
申请日：2001-10-11
申请人： Dean Liu , Tyler J. Thorp , Pradeep R. Trivedi , Gin S. Yee , Claude R. Gauthier
发明人： Dean Liu , Tyler J. Thorp , Pradeep R. Trivedi , Gin S. Yee , Claude R. Gauthier
IPC分类号： H03L706
CPC分类号： H03L7/07 , G06F1/10 , H03L7/0814
摘要： An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.
摘要翻译： 集成电路具有多个部分，每个部分具有相位检测器和控制延迟电路。 相位检测器响应于参考时钟信号和来自时钟网格的一部分的反馈信号之间的相位差来控制其关联的时钟延迟电路的延迟，其又输出到时钟网格的一部分 。 到相位检测器的反馈信号可以连接到DLL或由与相位检测器不相关的时钟延迟电路控制的时钟网格的另一部分的输出。 集成电路上的这种布置导致时钟网格偏移减少。
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公开(公告)号：US06662126B2
公开(公告)日：2003-12-09
申请号：US09930012
申请日：2001-08-14
申请人： Dean Liu , Gin S. Yee , Tyler J. Thorp , Pradeep R. Trivedi
发明人： Dean Liu , Gin S. Yee , Tyler J. Thorp , Pradeep R. Trivedi
IPC分类号： G06F1900
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and apparatus to determine skew of an on-chip signal without physical probing of the on-chip signal on the chip is provided. The method and apparatus use an externally generated reference signal that is distributed to one or more on-chip samplers that input the on-chip signal. Then, by modulating the externally generated reference signal, transitions of the on-chip signal can be detected at the one or more on-chip samplers so that the skew of the on-chip signal can be determined.
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公开(公告)号：US06618277B2
公开(公告)日：2003-09-09
申请号：US09930537
申请日：2001-08-14
IPC分类号： H02M700
摘要： An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.
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公开(公告)号：US06476663B1
公开(公告)日：2002-11-05
申请号：US09929151
申请日：2001-08-14
IPC分类号： H01L3500
CPC分类号： G01K7/00 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing power supply noise in the power supply system of a thermal sensor has been developed. The method includes powering up a thermal sensor and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the thermal sensor.
摘要翻译： 已经开发了用于降低热传感器的电源系统中的电源噪声的方法。 该方法包括加热热传感器并在电源端子上插入分流电阻。 分流电阻与热传感器并联插入。
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公开(公告)号：US06618845B2
公开(公告)日：2003-09-09
申请号：US09932191
申请日：2001-08-17
申请人： Tyler J. Thorp , Pradeep R. Trivedi , Dean Liu
发明人： Tyler J. Thorp , Pradeep R. Trivedi , Dean Liu
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for verifying on-chip decoupling capacitance by formulating and solving a linear problem. Further, a software tool for determining decoupling capacitance on a computer chip using a linear problem. Further, a method for designing an integrated circuit such that there is enough decoupling capacitance on the integrated circuit.
摘要翻译： 一种用于通过拟订和求解线性问题来验证片上去耦电容的方法。 此外，一种用于使用线性问题在计算机芯片上确定去耦电容的软件工具。 此外，一种用于设计集成电路的方法，使得在集成电路上存在足够的去耦电容。
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公开(公告)号：US06611573B2
公开(公告)日：2003-08-26
申请号：US09930051
申请日：2001-08-14
申请人： Pradeep R. Trivedi , Tyler J. Thorp , Dean Liu
发明人： Pradeep R. Trivedi , Tyler J. Thorp , Dean Liu
IPC分类号： H03K2100
CPC分类号： H03K23/68
摘要： A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.
摘要翻译： 提供了一种用于将信号频率除以非整数值的方法和装置。 此外，提供了一种通过计数信号的相位来将信号频率除以非整数值的方法和装置。
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7.发明授权公开(公告)号：US06501328B1
公开(公告)日：2002-12-31
申请号：US09930435
申请日：2001-08-14
IPC分类号： H03B100
CPC分类号： H03L7/0812
摘要： A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.
摘要翻译： 已经开发了用于减小延迟锁定环路的电源系统中的电源噪声的方法。 该方法包括上电延迟锁定环路，并在电源端子上插入分流电阻。 分流电阻与延迟锁定环并联插入。
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8.发明授权公开(公告)号：US06720813B1
公开(公告)日：2004-04-13
申请号：US10390286
申请日：2003-03-17
申请人： Gin S. Yee , Pradeep R. Trivedi , Joseph R. Siegel
发明人： Gin S. Yee , Pradeep R. Trivedi , Joseph R. Siegel
IPC分类号： H03K3037
CPC分类号： H03K3/037
摘要： A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.
摘要翻译： 提供可以独立于时钟信号可编程地复位的双边沿触发触发器。 使用外部产生的复位值，双边沿触发的触发器可以异步编程以复位为逻辑高或逻辑低电平。 此外，提供可以设置为多个触发模式的双边沿触发触发器。 使用外部产生的使能信号，双边沿触发触发器可以被设置为单边沿触发或双边沿触发器件。 因此，双边沿触发的触发器可以用于多种类型的计算环境。
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公开(公告)号：US07054787B2
公开(公告)日：2006-05-30
申请号：US10349854
申请日：2003-01-23
IPC分类号： G06F11/00
CPC分类号： G01R31/2829
摘要： A method and apparatus for sensing an aging effect on an integrated circuit using a sensor disposed on the integrated circuit and arranged to generate an output dependent on a condition of an element within the sensor. A processor operatively connected to the sensor is arranged to indicate a code dependent the output.
摘要翻译： 用于使用设置在集成电路上的传感器来感测对集成电路的老化效应的方法和装置，并且被布置成根据传感器内的元件的状况产生输出。 可操作地连接到传感器的处理器被布置成指示依赖于输出的代码。
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10.发明授权Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators 有权用于延迟锁定环和锁相环偏置发生器的负偏置温度不稳定性校正技术公开(公告)号：US06812758B2
公开(公告)日：2004-11-02
申请号：US10364881
申请日：2003-02-12
IPC分类号： H03L706
CPC分类号： H03L7/0891 , H03L7/0812 , H03L7/0893 , H03L7/18
摘要： A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.
摘要翻译： 偏置发生器调节系统根据集成电路中的负偏置温度不稳定性影响调整PLL或DLL偏置发生器。 偏置发生器调节系统使用老化的独立参考电路和偏置电路来可操作地调整偏置发生器，使得在集成电路的寿命期间发生的晶体管“老化”效应被补偿或校正。
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