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32 条记录 (耗时 0.026 秒)

    Dual edge-triggered flip-flop design with asynchronous programmable reset
    1.
    发明授权
    Dual edge-triggered flip-flop design with asynchronous programmable reset 有权
    具有异步可编程复位的双边沿触发触发器设计

    公开(公告)号：US06720813B1

    公开(公告)日：2004-04-13

    申请号：US10390286

    申请日：2003-03-17

    申请人： Gin S. Yee ,  Pradeep R. Trivedi ,  Joseph R. Siegel

    发明人： Gin S. Yee ,  Pradeep R. Trivedi ,  Joseph R. Siegel

    IPC分类号： H03K3037

    CPC分类号： H03K3/037

    摘要： A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.

    摘要翻译： 提供可以独立于时钟信号可编程地复位的双边沿触发触发器。 使用外部产生的复位值，双边沿触发的触发器可以异步编程以复位为逻辑高或逻辑低电平。 此外，提供可以设置为多个触发模式的双边沿触发触发器。 使用外部产生的使能信号，双边沿触发触发器可以被设置为单边沿触发或双边沿触发器件。 因此，双边沿触发的触发器可以用于多种类型的计算环境。

    Deskewing global clock skew using localized DLLs
    2.
    发明授权
    Deskewing global clock skew using localized DLLs 有权
    使用本地化DLL来消除全局时钟偏移

    公开(公告)号：US06686785B2

    公开(公告)日：2004-02-03

    申请号：US09975359

    申请日：2001-10-11

    申请人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    发明人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    IPC分类号： H03L706

    CPC分类号： H03L7/07 ,  G06F1/10 ,  H03L7/0814

    摘要： An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

    摘要翻译： 集成电路具有多个部分，每个部分具有相位检测器和控制延迟电路。 相位检测器响应于参考时钟信号和来自时钟网格的一部分的反馈信号之间的相位差来控制其关联的时钟延迟电路的延迟，其又输出到时钟网格的一部分 。 到相位检测器的反馈信号可以连接到DLL或由与相位检测器不相关的时钟延迟电路控制的时钟网格的另一部分的输出。 集成电路上的这种布置导致时钟网格偏移减少。

    Embedded integrated circuit aging sensor system
    3.
    发明授权
    Embedded integrated circuit aging sensor system 有权
    嵌入式集成电路老化传感器系统

    公开(公告)号：US07054787B2

    公开(公告)日：2006-05-30

    申请号：US10349854

    申请日：2003-01-23

    申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Gin S. Yee

    发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Gin S. Yee

    IPC分类号： G06F11/00

    CPC分类号： G01R31/2829

    摘要： A method and apparatus for sensing an aging effect on an integrated circuit using a sensor disposed on the integrated circuit and arranged to generate an output dependent on a condition of an element within the sensor. A processor operatively connected to the sensor is arranged to indicate a code dependent the output.

    摘要翻译： 用于使用设置在集成电路上的传感器来感测对集成电路的老化效应的方法和装置，并且被布置成根据传感器内的元件的状况产生输出。 可操作地连接到传感器的处理器被布置成指示依赖于输出的代码。

    Compensation technique to mitigate aging effects in integrated circuit components
    6.
    发明授权
    Compensation technique to mitigate aging effects in integrated circuit components 有权
    补偿技术，以减轻集成电路元件的老化效应

    公开(公告)号：US07129800B2

    公开(公告)日：2006-10-31

    申请号：US10771989

    申请日：2004-02-04

    申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Raymond A. Heald ,  Gin S. Yee

    发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Raymond A. Heald ,  Gin S. Yee

    IPC分类号： H03L1/00

    CPC分类号： H03L7/18 ,  G01R31/31727 ,  G06F2217/76 ,  H03L7/0812 ,  H03L7/0893

    摘要： A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

    摘要翻译： 一种用于补偿集成电路性能的年龄相关退化的方法和装置。 在一个实施例中，锁相环（PLL）电荷泵设置有多个支脚，其可以选择性地启用或禁用以补偿老化的影响。 在替代实施例中，可以增加或减少电源电压控制代码以补偿老化效应。 在另一个实施例中，环形振荡器用于近似NBTI的影响。 在本实施例中，使用数字计数器将频域转换为时域，并且使用可编程电源控制字来改变电源的操作参数以补偿老化效应。

    DLL static phase error measurement technique
    8.
    发明授权
    DLL static phase error measurement technique 有权
    DLL静态相位误差测量技术

    公开(公告)号：US06829548B2

    公开(公告)日：2004-12-07

    申请号：US10406541

    申请日：2003-04-03

    申请人： Priya Ananthanarayanan ,  Pradeep R. Trivedi ,  Claude R. Gauthier

    发明人： Priya Ananthanarayanan ,  Pradeep R. Trivedi ,  Claude R. Gauthier

    IPC分类号： G06F1100

    CPC分类号： H03L7/0812 ,  G01R25/005

    摘要： An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.

    摘要翻译： 用于测量延迟锁定环路中的静态相位误差的装置包括第一测试阶段和第二测试阶段。 第一测试阶段接收参考时钟，芯片时钟和控制信号。 与第一测试级并行，第二测试级接收参考时钟，芯片时钟和控制信号的补码。 根据控制信号，第一测试级输出第一测试信号，并且根据控制信号的补码，第二测试级输出第二测试信号。 第一测试信号和第二测试信号用于根据控制信号和控制信号的补码产生一组静态相位误差测量值。 通过对静态相位误差测量值进行平均，对延迟锁定环路测量静态相位误差。

    Programmable current source adjustment of leakage current for phase locked loop
    9.
    发明授权
    Programmable current source adjustment of leakage current for phase locked loop 有权
    锁相环漏电流可编程电流源调节

    公开(公告)号：US06570423B1

    公开(公告)日：2003-05-27

    申请号：US10230596

    申请日：2002-08-29

    申请人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Sudhakar Bobba

    发明人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Sudhakar Bobba

    IPC分类号： H03L706

    CPC分类号： H03L7/0893 ,  H03L7/18

    摘要： A method and apparatus for post-fabrication adjustment of a phased locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the phased locked loop allows a designer to achieve a desired phase locked loop operating characteristic after fabrication of the adjustable phase locked loop.

    摘要翻译： 提供了一种用于相位锁定环路漏电流的制造后调整的方法和装置。 调节系统包括一个可编程电流源，调节漏电流补偿电路以补偿电容器的漏电流。 电容器连接到锁相环的控制电压。 可编程电流源包括至少一个电流源和用于调整漏电流补偿电路的开关。 可编程电流源由组合逻辑电路选择性地调节。 对相位锁定环中的漏电流的这种控制允许设计者在制造可调锁相环之后实现期望的锁相环工作特性。

    Programmable current source adjustment of leakage current for delay locked loop
    10.
    发明授权
    Programmable current source adjustment of leakage current for delay locked loop 有权
    用于延迟锁定环路的可编程电流源调节漏电流

    公开(公告)号：US06570420B1

    公开(公告)日：2003-05-27

    申请号：US10230649

    申请日：2002-08-29

    申请人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Dean Liu

    发明人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Dean Liu

    IPC分类号： H03L706

    CPC分类号： H03L7/0891 ,  H03L7/0812

    摘要： A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.

    摘要翻译： 提供了延迟锁定环路漏电流的制造后调整方法和装置。 调节系统包括一个可编程电流源，调节漏电流补偿电路以补偿电容器的漏电流。 电容器连接到延迟锁定环路的控制电压。 可编程电流源包括至少一个电流源和用于调整漏电流补偿电路的开关。 可编程电流源由组合逻辑电路选择性地调节。 对延迟锁定环路中的漏电流的这种控制允许设计者在制造可调延迟锁定环路之后实现期望的延迟锁定环路工作特性。