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1.发明授权公开(公告)号：US06631428B1
公开(公告)日：2003-10-07
申请号：US09562489
申请日：2000-05-01
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： A mechanism that includes an apparatus and method for ensuring that all transactions within any flow control class completes is herein provided. The mechanism includes a plunge transaction that is inserted in each pending transaction queue and which is transmitted to a particular destination device. All prior transactions in a flow control class are deemed to be complete when the destination device receives the plunge transactions in the flow control class.
摘要翻译： 这里提供了一种机制，其包括用于确保任何流控制类中的所有事务完成的装置和方法。 该机制包括插入到每个挂起的事务队列中的插入事务，并将其发送到特定目的地设备。 当目标设备在流控制类中接收到插入事务时，流控制类中的所有先前事务被认为是完整的。
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2.发明授权Method and apparatus for preventing underflow and overflow across an asynchronous channel 有权用于防止异步通道下溢和溢出的方法和装置公开(公告)号：US06813275B1
公开(公告)日：2004-11-02
申请号：US09556052
申请日：2000-04-21
IPC分类号： H04L1256
CPC分类号： G06F13/387 , H04L7/005 , H04L2007/045
摘要： An apparatus and method for an improved asynchronous communication channel between a transmitter and a receiver having separate clocks. The invention provides a simple implementation that solves both the overflow and the underflow problem using the same mechanism, and reduces complexity by elimination of the control split between the two clock domains. A first embodiment of the invention is a method for preventing packet underflow and packet overflow for packets sent across an asynchronous link between a transmitter and a receiver, including a buffer that can store a number of packets greater than an ideal number of packets. The method includes sending a predetermined number of drop-me warning packets and sending one or more drop-me packets from the transmitter to the receiver, receiving the predetermined number of drop-me warning packets and the one or more drop-me packets in the buffer, compensating for packet overflow when the number of packets is greater than the ideal number of packets in the buffer by skipping at least one drop-me packet, and compensating for packet underflow in the buffer when the number of packets is less than the ideal number of packets by stalling access to the buffer for one or more clock cycles. A second embodiment of the invention is an asynchronous link for packets sent between a transmitter having a first clock and a receiver having a second clock, including a buffer to receive the first clock from the transmitter and receive from the transmitter a number of packets equal to or different to a predetermined ideal number of packets, a write pointer, and a read pointer, and a read pointer control circuit to change the read pointer, wherein the buffer can receive drop-me packets, and the read pointer can skip a drop-me packet in the buffer.
摘要翻译： 一种用于在具有单独时钟的发射机和接收机之间改进的异步通信信道的装置和方法。 本发明提供了使用相同机制解决溢出和下溢问题的简单实现，并且通过消除两个时钟域之间的控制分割来降低复杂度。 本发明的第一实施例是一种用于防止在发射机和接收机之间的异步链路上发送的分组的分组下溢和分组溢出的方法，包括可以存储大于理想数目分组的分组数量的缓冲器。 该方法包括发送预定数量的丢包警告包，并从发送器发送一个或多个丢包信息包到接收器，接收预定数量的丢包警告包和一个或多个丢包信息包 缓冲器，当数据包的数量大于缓冲器中理想数量的数据包时，通过跳过至少一个丢包分组来补偿数据包溢出，并且当数据包数量小于理想值时补偿缓冲器中的数据包下溢 数据包的数量通过停止访问缓冲区一个或多个时钟周期。 本发明的第二实施例是在具有第一时钟的发射机和具有第二时钟的接收机之间发送的分组的异步链路，包括缓冲器，用于从发射机接收第一时钟，并从发射机接收等于 或者不同于预定理想数量的分组，写指针和读指针，以及读指针控制电路，以改变读指针，其中缓冲器可以接收丢包，并且读指针可以跳过下拉菜单， 我在缓冲区中的数据包。
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3.发明授权Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware 失效具有重复测试事件生成硬件的计算机系统处理器到存储器总线接口
公开(公告)号：US5958072A
公开(公告)日：1999-09-28
申请号：US782964
申请日：1997-01-13
CPC分类号： G06F11/2273 , G06F11/221
摘要： A processor-to-memory interface (PMI) for a multiprocessor computer system and a computer testing method are disclosed. The multi-processor computer system provides a processor-to-memory-bus interface for each microprocessor. Each processor-to-memory-bus interface translates between microprocessor and bus protocols and manages respective level-2 (L2) caches. In addition, each interface includes test-event hardware that, when enabled causes test events to be generated with a predetermined repetition rate. The test events are selected for having a non-zero probability of causing system events that are complex, rare and non-fatal. These include assertions of "busy" and "wait" conditions and corrections of single-bit cache errors. The test-event hardware includes a timing generator that determines when test events are to be generated, an event-flag register that determines which events are to be generated, and a test-event generator that generates test-events at the times determined by the timing generator. The timing generator can include a down counter and a register for holding a value to be entered into the counter upon initialization and reset. So that cache error-correction logic can be tested, a cache manager includes a cache-error generator that can generate cache errors at times determined by said timing generator. The test-event hardware permits system events of interest to be repeatedly generated during a test procedure without repeated intervention by a test program. The hardware test-event generation simplifies test program design and allows faster testing throughput.
摘要翻译： 公开了一种用于多处理器计算机系统的处理器到存储器接口（PMI）和计算机测试方法。 多处理器计算机系统为每个微处理器提供处理器到存储器总线接口。 每个处理器到存储器总线接口在微处理器和总线协议之间进行转换，并管理相应的二级（L2）高速缓存。 另外，每个接口包括测试事件硬件，当被使能时，可以以预定的重复率生成测试事件。 选择测试事件具有导致复杂，罕见和非致命的系统事件的非零概率。 这些包括断言“忙”和“等待”条件和单位缓存错误的更正。 测试事件硬件包括一个定时发生器，用于确定何时生成测试事件，事件标志寄存器确定要生成哪些事件;以及测试事件发生器，其在由 定时发生器 定时发生器可以包括向下计数器和用于在初始化和复位时保持要输入到计数器中的值的寄存器。 因此，可以测试高速缓存错误校正逻辑，高速缓存管理器包括高速缓存错误发生器，其可以在由所述定时发生器确定的时间内产生高速缓存错误。 测试事件硬件允许感兴趣的系统事件在测试过程中重复产生，而不需要测试程序的反复干预。 硬件测试事件生成简化了测试程序设计，并允许更快的测试吞吐量。
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4.发明授权Wait state mechanism for a high speed bus which allows the bus to continue running a preset number of cycles after a bus wait is requested 失效一个高速总线的等待状态机制，允许总线在请求总线等待后继续运行预设的循环次数
公开(公告)号：US5339440A
公开(公告)日：1994-08-16
申请号：US933434
申请日：1992-08-21
CPC分类号： G06F13/4217
摘要： The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.
摘要翻译： 本发明提供了一种在数字计算机中等待总线的协议方法和用于实现该协议的装置。 通过允许总线在等待命令被断言之后继续运行，计算机总线上的模块不需要立即响应等待命令。 在等待期间的多个周期内，总线上的信息被定义为无效，等待期结束后在总线上驱动有效的数据。 总线驱动器模块具有重播队列，用于在总线上播放驱动程序模块在等待期间在总线上驱动的数据（如果需要）。
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公开(公告)号：US20140007523A1
公开(公告)日：2014-01-09
申请号：US13934952
申请日：2013-07-03
申请人： Mark Hugh Fairbairn , Nathan Paul Perkins , Edward M. Jacobs , David Joseph Nahlen , Richard Morgan Slocum
发明人： Mark Hugh Fairbairn , Nathan Paul Perkins , Edward M. Jacobs , David Joseph Nahlen , Richard Morgan Slocum
IPC分类号： F15D1/10
CPC分类号： F15D1/10 , E04H12/10 , E04H12/20 , H02G7/20 , Y10T29/49826
摘要： A modular strake for reducing the effects of wind on utility structures is disclosed. The strake is comprised of individual fin sections that may easily be attached to a utility structure, preferably in a triple helix pattern. The modular strakes may be installed on a utility structure after is has been placed into service.
摘要翻译： 公开了一种用于减小风对效用结构的影响的模块化行星。 板条由单独的翅片部分组成，其可以容易地附接到效用结构，优选地是三螺旋图案。 已投入使用后，模块化的散热片可能安装在公用事业结构上。
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6.发明授权公开(公告)号：US07307635B1
公开(公告)日：2007-12-11
申请号：US10906091
申请日：2005-02-02
申请人： Jimmy Yang , Bo Ye , Edward M. Jacobs
发明人： Jimmy Yang , Bo Ye , Edward M. Jacobs
CPC分类号： G09G5/37 , G09G5/393 , G09G2340/0492
摘要： A frame buffer stores X pixels per line and Y lines and is read using a burst of B pixels. The un-rotated image is rotated by 90 degrees for display by writing and reading pixels from a line buffer. The line buffer stores a block of B*Y pixels. The frame buffer is logically divided into X/B blocks that are B pixels wide. Blocks are read from the frame buffer from the bottom line to the top with a burst of B pixels per line. An offset locate pixels to read in the line buffer. The offset is B for the first block, and increases by a factor of B for each block read, but wraps around modulo B*Y−1. Pixels for a next block are written into the line buffer to locations vacated as pixels are read out. The increasing offset re-orders the pixels for the rotated display order.
摘要翻译： 帧缓冲器存储每行X行和Y行，并使用B像素的脉冲串进行读取。 通过从行缓冲区中写入和读取像素，未旋转的图像旋转90度以进行显示。 行缓冲器存储一组B * Y像素。 帧缓冲器在逻辑上被划分为B像素宽的X / B块。 块从帧缓冲区从底行到顶部读取，每行具有B个像素的突发。 偏移量定位要在行缓冲区中读取的像素。 第一个块的偏移量为B，对于每个块读取增加一个因子B，而是围绕模B * Y-1。 下一个块的像素被写入行缓冲器到读出像素的位置。 增加的偏移重新排列旋转显示顺序的像素。
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7.发明授权Method and apparatus for maintaining duplicate cache tags with selectable width 失效用于维持可选宽度的重复缓存标签的方法和装置
公开(公告)号：US5907853A
公开(公告)日：1999-05-25
申请号：US783918
申请日：1997-01-17
申请人： Edward M. Jacobs , Julie W. Moncton
发明人： Edward M. Jacobs , Julie W. Moncton
CPC分类号： G06F12/0831
摘要： A multiprocessor computer architecture containing processor caches that are kept coherent, and in particular, a duplicate cache tag subsystem and method for maintaining duplicate cache tags, are disclosed. The tag width of duplicate cache tags for a processor cache is tailored to available integrated circuit surface area, or to device pin count, without significantly sacrificing system performance. Such partial duplicate tag width may also be reduced at any time during the integrated circuit design phase, should the available integrated circuit surface area or pin-availability decrease. The method disclosed involves requesting data from memory; reading a partial duplicate cache tag list to determine if there is a partial hit; taking the data from the memory if there is no match between a requested address and the partial duplicate cache tag list; holding the data in memory or a requestor module if there is a match between the requested address and the partial duplicate cache tag list; and interrupting processor operation to confirm that the partial duplicate cache tag corresponds to an actual cache tag. The data are taken from the cache if the partial duplicate cache tag matches the actual cache tag and cache status indicates that the data have been modified. The data are taken from memory if the partial duplicate cache tag does not match the actual cache tag or cache status indicates that the data have not been modified.
摘要翻译： 公开了包含保持一致的处理器高速缓存的多处理器计算机体系结构，特别是用于维护重复的高速缓存标签的重复的高速缓存标签子系统和方法。 处理器高速缓存的重复高速缓存标签的标签宽度是针对可用的集成电路表面积或设备引脚数而定制的，而不会显着降低系统性能。 如果可用的集成电路表面积或引脚可用性降低，则集成电路设计阶段期间的任何时间也可以减少这种部分重复标签宽度。 所公开的方法涉及从存储器请求数据; 读取部分重复缓存标签列表以确定是否存在部分命中; 如果所请求的地址和部分重复缓存标签列表之间没有匹配，则从存储器获取数据; 如果所请求的地址和部分重复缓存标签列表之间存在匹配，则将数据保存在存储器或请求者模块中; 并且中断处理器操作以确认部分重复缓存标签对应于实际的高速缓存标签。 如果部分重复缓存标签与实际高速缓存标签匹配，则从缓存中获取数据，缓存状态表示数据已被修改。 如果部分重复缓存标签与实际缓存标记不匹配或高速缓存状态表示数据未被修改，则从内存中获取数据。
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