公开(公告)号：US5943243A

公开(公告)日：1999-08-24

申请号：US739142

申请日：1996-10-28

申请人： Deepak D. Sherlekar ,  Craig R. Selinger

发明人： Deepak D. Sherlekar ,  Craig R. Selinger

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Disclosed is a method and system for removing hardware overlap for use with a computer aided design apparatus. The method and system remove overlap by separately classifying all free blocks and blocks fixed in place, and then shifting cells between free blocks while maintaining the same relative ordering of the cells. Thus, all move bounds are respected and only cells that exist in free blocks actually move. The operation takes place one partition at a time, whereby a typical partition includes a row of cells.

摘要翻译： 公开了一种用于去除与计算机辅助设计装置一起使用的硬件重叠的方法和系统。 方法和系统通过单独分类固定的所有空闲块和块来去除重叠，然后在保持单元的相同相对顺序的同时在移动块之间移动小区。 因此，所有移动边界都被尊重，并且只有存在于空闲块中的单元实际上移动。 该操作一次发生一个分区，其中典型的分区包括一行单元格。

公开(公告)号：US5507029A

公开(公告)日：1996-04-09

申请号：US371329

申请日：1995-01-11

申请人： Michael A. Granato ,  Gregory F. Miceli ,  Jerome R. Relis ,  Craig R. Selinger ,  Vernon L. Watts

发明人： Michael A. Granato ,  Gregory F. Miceli ,  Jerome R. Relis ,  Craig R. Selinger ,  Vernon L. Watts

IPC分类号： F02B75/02 ,  G06F1/10 ,  G06F17/50 ,  G06F15/60

CPC分类号： G06F1/10 ,  G06F17/5077 ,  F02B2075/027

摘要： A method for minimizing the time skew between signals traveling through various multi-cycle path nets linking one or several VLSI packages that includes a plurality of IC chips interconnected to each other. The method includes equalizing differences between the early and the late mode slack for each of the multi-cycle nets to decrease the joint probability of failure; maximizing the time balance between the early and the late mode slack; balancing over all the nets the difference between the early and the late mode slack, minimizing in the process statistical variations within the mode slack pair; and compensating for asymmetries between rising and falling switching times using the mode slack pair. The method allows multi-cycle path nets have their transmission line length confined between a maximum and a minimum length, which in turn minimizes the skew between signals in each of the nets, decreases cycle time and .improves the overall performance of the system.

摘要翻译： 一种用于最小化穿过各种多循环路径网络的信号之间的时间偏移的方法，所述多个循环路径网络链接包括彼此互连的多个IC芯片的一个或多个VLSI封装。 该方法包括均衡每个多周期网络的早期和晚期模式松弛之间的差异，以降低联合故障概率; 最大化早期和晚期模式之间的时间平衡松弛; 平衡所有的网络早期和晚期模式之间的差异松弛，最大限度地减少模式松弛对内的统计变化; 并使用模式松弛对来补偿上升和下降切换时间之间的不对称性。 该方法允许多周期路径网络将其传输线路长度限制在最大和最小长度之间，从而最大限度地减少每个网络中的信号之间的偏差，减少周期时间和改善系统的整体性能。

公开(公告)号：US5477460A

公开(公告)日：1995-12-19

申请号：US360519

申请日：1994-12-21

申请人： Charles K. Vakirtzis ,  George A. Katopis ,  Gerald W. Mahoney ,  Craig R. Selinger ,  Bradley D. McCredie ,  Wiren D. Becker

发明人： Charles K. Vakirtzis ,  George A. Katopis ,  Gerald W. Mahoney ,  Craig R. Selinger ,  Bradley D. McCredie ,  Wiren D. Becker

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle. The height of the triangle, as well as the pitch of the sides of the triangle will be determined by the characteristics of the net. In the early stages of design, a default characteristic triangle is defined for each technology type. A general triangle is also defined for cases where early analysis needs to be performed prior to choosing a technology.

摘要翻译： 系统组件的开关特性被表示和相加，以便在设计过程中可以观察到它们对整个系统的影响。 通过计算基于网络的同步开关噪声电平的方法，提供了最初设计的包含最小级别的设计数据的全面同步开关分析，该方法支持从最小芯片级到最大板级的封装。 基于每个组件和每个其他组件之间的每个驱动程序和每个其他驱动程序之间的相互作用计算同时切换活动，考虑到较高级组件内的空间相互关系网，以确定每个组件的驱动程序对其本身的影响 作为不同组件上的驱动程序之间的耦合效应。 分析涉及通过将特征三角形与每个驱动程序应用程序配置相关联来计算同时切换噪声。 特征三角形。 三角形的高度以及三角形边的间距将由网络的特性决定。 在设计的早期阶段，为每种技术类型定义默认特征三角形。 对于在选择技术之前需要进行早期分析的情况，也定义了一般三角形。

公开(公告)号：US5544088A

公开(公告)日：1996-08-06

申请号：US492415

申请日：1995-06-19

申请人： Matthew E. Aubertine ,  Kianoush Beyzavi ,  Harold J. Broker ,  Ronald P. Checca ,  Michael A. Granato ,  David A. Haeussler ,  Michael Herasimtschuk ,  Michael J. Jurkovic ,  Gerard M. Salem ,  Craig R. Selinger ,  Paul R. Zehr

发明人： Matthew E. Aubertine ,  Kianoush Beyzavi ,  Harold J. Broker ,  Ronald P. Checca ,  Michael A. Granato ,  David A. Haeussler ,  Michael Herasimtschuk ,  Michael J. Jurkovic ,  Gerard M. Salem ,  Craig R. Selinger ,  Paul R. Zehr

IPC分类号： G06F13/40 ,  G06F17/50 ,  G06F15/17 ,  G06F11/26

CPC分类号： G06F13/4072 ,  G06F17/5072

摘要： A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level. I/Os assignment by this method for a computer system package design reduces the occurance of any critical nets failing length, electrical or timing constraints due to poor I/O assignments. The method has built in checks to avoid being trapped in an NP complete situation (a form of endless loop).

摘要翻译： 提供了一种方法来为计算机系统的每个级别的所有组件分配组件I / O（输入/输出，物理封装级别之间的接口面积）引脚。 在分层的自上而下的设计方法中，每个计算机系统组件的I / O引脚分配给网络（网络是包装级别的引脚或封装层级之间的互连），基于导线长度，电气 限制和时间安排 被考虑的参数是网络优先级（该网络对系统的相对于系统中的其他网络的重要性），物理组件的位置，物理组件I / O在物理包装层次结构的所有计算机系统级别的位置，以及I / O引脚特性。 使用迭代方法根据时序分配和重新分配每个级别的I / O引脚。 由于I / O在每个较低的组件级别重新分配，所以根据较低级别的已更改参数在系统打包层次结构的所有较高级别进行新的分配。 通过该方法对计算机系统软件包设计进行的I / O分配可以减少由于I / O分配不良导致的任何关键网络发生长度，电气或时序限制的故障。 该方法已经内置了检查，以避免被困在NP完全情况（一种无止境循环的形式）中。

公开(公告)号：US6014508A

公开(公告)日：2000-01-11

申请号：US909112

申请日：1997-08-11

申请人： Kenneth L. Christian ,  Craig R. Selinger ,  Hope L. Bauer ,  Hardev S. Dhaliwal ,  Cynthia L. Martin

发明人： Kenneth L. Christian ,  Craig R. Selinger ,  Hope L. Bauer ,  Hardev S. Dhaliwal ,  Cynthia L. Martin

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method of wiring a plurality of integrated circuits within a chip or between chips in one or more packages by adding cluster points to a net that includes a plurality of nodes to be interconnected. The interconnected nodes are designed to meet system requirements, commonly expressed by a set of wiring rules, include among others, physical, electrical and noise constraints. The method includes matching interconnection net attributes to wiring rule logical definitions, wherein the wiring rules include rule nodes and rule connections. The rule nodes define constraints for the pins, vias and cluster point structures. The rule connections define wiring constraints between the node structures to establish the net topology. The process described is based on net ordering and checking. The net ordering, which defines the pin-to-pin connections based on the wiring rule, is performed prior to chip or package wiring. Net ordering imposes the wiring rule added cluster points, the desired interconnection topology and the wiring constraints to the net. Checking verifies the correctness of the net attributes when the design wiring is complete.

摘要翻译： 一种通过向包括要互连的多个节点的网络添加集群点来在一个或多个包装中的芯片内或芯片之间布线多个集成电路的方法。 互连节点被设计为满足系统要求，通常由一组布线规则表示，包括物理，电气和噪声限制。 该方法包括将互连网络属性与布线规则逻辑定义相匹配，其中布线规则包括规则节点和规则连接。 规则节点定义了引脚，通孔和簇点结构的约束。 规则连接定义节点结构之间的布线约束以建立网络拓扑。 所描述的过程是基于网络排序和检查。 基于布线规则定义引脚到引脚连接的网络排序在芯片或封装布线之前执行。 网络排序强制布线规则添加了集群点，所需的互连拓扑和布线约束到网络。 当设计接线完成时，检查会验证网络属性的正确性。

公开(公告)号：US5757653A

公开(公告)日：1998-05-26

申请号：US648800

申请日：1996-05-16

申请人： Kenneth L. Christian ,  Timothy A. Schell ,  Craig R. Selinger

发明人： Kenneth L. Christian ,  Timothy A. Schell ,  Craig R. Selinger

IPC分类号： H01L23/12 ,  G06F17/50

CPC分类号： G06F17/509 ,  G06F17/5077

摘要： Permutations of orders of elements such as electrical connection pins, vias and t-junctions at known locations are efficiently tested against at least type and distance criteria by forming a plurality of lists of the elements and screening the elements of each list against respective ones of said type criteria to reduce the length of the lists of elements. Pointers to ones of the distance criteria and remaining members of a list corresponding to respective ones of the distance criteria iteratively form pairs of elements which are checked for separation. When the check fails or a solution is found, the pointer to list members is advanced. The pointer to respective distance criteria is advanced when a check is successful. When a list is exhausted and a check is unsuccessful, the pointer to respective distance criteria is regressed. Advancement and regression of pointers reduces iterations of combinations of pairs of elements which do not lead to a solution in order to accelerate the process. Each new solution is evaluated against a single stored prior solution for optimization of solutions while greatly reducing storage requirements.

摘要翻译： 通过形成多个元件列表并根据相应的所述元件筛选每个列表的元素，来有效地对至少类型和距离标准来测试已知位置处的诸如电连接引脚，通孔和T形接头之类的元件的顺序的排列 键入标准以减少元素列表的长度。 指向距离标准中的一个的指针和与各个距离标准相对应的列表的剩余成员迭代地形成检查分离的元素对。 当检查失败或找到解决方案时，指向列表成员的指针是高级的。 当检查成功时，指向相应距离标准的指针会提前。 当列表用尽并且检查不成功时，指向相应距离标准的指针被退化。 指针的推进和回归减少了不会导致解决方案的元素对的组合的迭代，以加速过程。 每个新解决方案都针对单一存储的先前解决方案进行评估，以优化解决方案，同时大大减少存储要求。