公开(公告)号：US20120081963A1

公开(公告)日：2012-04-05

申请号：US12894889

申请日：2010-09-30

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.

摘要翻译： 在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。 在随后的程序验证迭代中，锁定的存储元件进行全通道升压。 或者，在锁定之后，可以通过多次程序验证迭代来加强升压。 可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。 对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

公开(公告)号：US08134871B2

公开(公告)日：2012-03-13

申请号：US12536127

申请日：2009-08-05

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

摘要翻译： 根据其WLn-1相邻存储元件的状态，通过在分离的组中对所选字线WLn上的存储元件进行编程来对非易失性存储系统中的程序干扰进行减少，并且对于每一个，向WLn-1施加最佳的通过电压 组。 最初，读取WLn-1上的存储元件的状态。 程序迭代包括多个程序脉冲。 当向WLn-1施加第一通过电压时，将第一编程脉冲施加到WLn，选择第一组WLn存储元件进行编程，并且禁止第二组WLn存储元件。 接下来，向WLn施加第二编程脉冲，同时将第二通过电压施加到WLn-1，选择第二组WLn存储元件进行编程，并且禁止第一组WLn存储元件。 组可以包括一个或多个数据状态。

公开(公告)号：US20110032757A1

公开(公告)日：2011-02-10

申请号：US12536127

申请日：2009-08-05

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

摘要翻译： 根据其WLn-1相邻存储元件的状态，通过在分离的组中对所选字线WLn上的存储元件进行编程来对非易失性存储系统中的程序干扰进行减少，并且对于每一个，向WLn-1施加最佳的通过电压 组。 最初，读取WLn-1上的存储元件的状态。 程序迭代包括多个程序脉冲。 当向WLn-1施加第一通过电压时，将第一编程脉冲施加到WLn，选择第一组WLn存储元件进行编程，并且禁止第二组WLn存储元件。 接下来，向WLn施加第二编程脉冲，同时将第二通过电压施加到WLn-1，选择第二组WLn存储元件进行编程，并且禁止第一组WLn存储元件。 组可以包括一个或多个数据状态。

公开(公告)号：US08369149B2

公开(公告)日：2013-02-05

申请号：US12894889

申请日：2010-09-30

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.

摘要翻译： 在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。 在随后的程序验证迭代中，锁定的存储元件进行全通道升压。 或者，在锁定之后，可以通过多次程序验证迭代来加强升压。 可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。 对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

公开(公告)号：US20100034022A1

公开(公告)日：2010-02-11

申请号：US12188629

申请日：2008-08-08

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418

摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

摘要翻译： 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻的存储元件。

公开(公告)号：US08320177B2

公开(公告)日：2012-11-27

申请号：US13370410

申请日：2012-02-10

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

公开(公告)号：US20120140568A1

公开(公告)日：2012-06-07

申请号：US13370410

申请日：2012-02-10

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

摘要翻译： 根据其WLn-1相邻存储元件的状态，通过在分离的组中对所选字线WLn上的存储元件进行编程来对非易失性存储系统中的程序干扰进行减少，并且对于每一个，向WLn-1施加最佳的通过电压 组。 最初，读取WLn-1上的存储元件的状态。 程序迭代包括多个程序脉冲。 当向WLn-1施加第一通过电压时，将第一编程脉冲施加到WLn，选择第一组WLn存储元件进行编程，并且禁止第二组WLn存储元件。 接下来，向WLn施加第二编程脉冲，同时将第二通过电压施加到WLn-1，选择第二组WLn存储元件进行编程，并且禁止第一组WLn存储元件。 组可以包括一个或多个数据状态。

公开(公告)号：US07876611B2

公开(公告)日：2011-01-25

申请号：US12188629

申请日：2008-08-08

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418

摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

摘要翻译： 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻存储元件。

公开(公告)号：US20110309426A1

公开(公告)日：2011-12-22

申请号：US13163538

申请日：2011-06-17

申请人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

摘要翻译： 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

公开(公告)号：US20110286265A1

公开(公告)日：2011-11-24

申请号：US12785636

申请日：2010-05-24

申请人： Nima Mokhlesi ,  Henry Chin ,  Masaaki Higashitani

发明人： Nima Mokhlesi ,  Henry Chin ,  Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10

摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.

摘要翻译： 用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。 编程过程包括为连接一组连接的非易失性存储元件的一组字线提升电压。 所述字线组包括所选择的字线，与所选字线和其它未选字线相邻的未选字线。 在提高该组字线的电压之后，该处理包括将所选择的字线升高到编程电压，并将与所选择的字线相邻的未选字线与提升所选择的字线同时提高到一个或多个电压电平 到程序电压。 程序电压使至少一个非易失性存储元件经历编程。