Runtime configuration of chipset to support multiple I/O subsystem versions with one BIOS image

    公开(公告)号:US11816491B2

    公开(公告)日:2023-11-14

    申请号:US17375911

    申请日:2021-07-14

    CPC classification number: G06F9/4411 G06F13/4282 G06F2213/0042

    Abstract: A method for configuring a peripheral bus of an information handling system performs, as part of a boot sequence, an initial configuration of a chipset setting pertaining to the bus based on a descriptor stored in a nonvolatile storage resource. After an operating system is loaded, a controller detects a peripheral device connecting to the bus and responds by performing a runtime configuration of the chipset setting based on capability information obtained from the peripheral device. The peripheral bus may comprise a USB pipe and a USB-C type connector, wherein the peripheral device is detected by a USB power delivery (PD) controller based on configuration channel (CC) pins of the USB-C connector. The PD controller may signal the chipset and send the device’s capability information to the chipset. The PD controller may assert a PMCALERT# signal of the chipset’s and send the capability information via a system management link (SMLink1).

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