公开(公告)号：US11334130B1

公开(公告)日：2022-05-17

申请号：US16952467

申请日：2020-11-19

Applicant: Dell Products L.P.

Inventor： Jeffrey L. Kennedy ,  Timothy M. Lambert ,  Yuchen Xu

IPC: G06F1/26 ,  G06F13/42 ,  G06F1/28 ,  G06F1/30 ,  G06F1/3206 ,  G06F1/18 ,  G06F9/02 ,  G06F9/4401

Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.

公开(公告)号：US11349965B1

公开(公告)日：2022-05-31

申请号：US17124774

申请日：2020-12-17

Applicant: Dell Products L.P.

Inventor： Yuchen Xu ,  Timothy M. Lambert ,  Jeffrey L. Kennedy

IPC: H04L69/22 ,  H01B13/34 ,  H04L69/24

Abstract: A system may include a controller, an endpoint device, and a cable coupled between the controller and the endpoint device and comprising a communication wire for bidirectionally communicating signals between the controller and the endpoint device and a circuit formed as a part of the cable and communicatively coupled to the communication wire, the circuit having a microcontroller unit configured to communicate identifying information regarding the cable to the controller via the communication wire and without contention with the signals bidirectionally communicated between the controller and the endpoint device.

公开(公告)号：US20220155834A1

公开(公告)日：2022-05-19

申请号：US16952467

申请日：2020-11-19

Applicant: Dell Products L.P.

Inventor： Jeffrey L. Kennedy ,  Timothy M. Lambert ,  Yuchen Xu

IPC: G06F1/26 ,  G06F13/42

Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.