公开(公告)号：US11899600B2

公开(公告)日：2024-02-13

申请号：US17583604

申请日：2022-01-25

Applicant: Dell Products L.P.

Inventor： Timothy M. Lambert ,  Jeffrey L Kennedy

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/382 ,  G06F13/4282 ,  G06F2213/0012 ,  G06F2213/0042 ,  G06F2213/38

Abstract: A serial connector adapter system includes a serial connector adapter device connected to a computing device. The serial connector adapter device includes a serial communication request subsystem coupled to a serial connector and a first USB connector. The computing device includes a second USB connector connected to the first USB connector, a serial communication subsystem coupled to the second USB connector, and a serial communication configuration subsystem coupled to the second USB connector and the serial communication subsystem. The serial communication configuration uses a USB ground drain connection in the first and second USB connectors subsystems to identify the serial connector adapter device and perform bi-directional communications to receive a request for serial communications with the serial communication subsystem and, in response, configures the serial communication subsystem to perform serial communications via the serial connector using USB transmitter/receiver pair connections in the first and second USB connectors.

公开(公告)号：US20240004447A1

公开(公告)日：2024-01-04

申请号：US18468771

申请日：2023-09-18

Applicant: Dell Products, L.P.

Inventor： Akkiah Choudary Maddukuri ,  Timothy M. Lambert ,  Elie Antoun Jreij ,  Bhavesh Govindbhai Patel ,  Mukund P. Khatri

IPC: G06F1/26 ,  G06F9/48

CPC classification number: G06F1/26 ,  G06F9/4893 ,  G06F11/3062

Abstract: Embodiments of systems and methods for power throttling of High Performance Computing (HPC) components are described. In some embodiments, an HPC platform may include: a system Baseboard Management Controller (BMC), and an accelerator tray comprising a tray BMC coupled to a plurality of managed subsystems and to the system BMC, where the system BMC is configured to: in response to a power excursion event, instruct the tray BMC to throttle a first managed subsystem by a first amount and to throttle a second managed subsystem by a second amount.

公开(公告)号：US20230237001A1

公开(公告)日：2023-07-27

申请号：US17583604

申请日：2022-01-25

Applicant: Dell Products L.P.

Inventor： Timothy M. Lambert ,  Jeffrey L. Kennedy

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/382 ,  G06F13/4282 ,  G06F2213/0012 ,  G06F2213/0042 ,  G06F2213/38

Abstract: A serial connector adapter system includes a serial connector adapter device connected to a computing device. The serial connector adapter device includes a serial communication request subsystem coupled to a serial connector and a first USB connector. The computing device includes a second USB connector connected to the first USB connector, a serial communication subsystem coupled to the second USB connector, and a serial communication configuration subsystem coupled to the second USB connector and the serial communication subsystem. The serial communication configuration uses a USB ground drain connection in the first and second USB connectors subsystems to identify the serial connector adapter device and perform bi-directional communications to receive a request for serial communications with the serial communication subsystem and, in response, configures the serial communication subsystem to perform serial communications via the serial connector using USB transmitter/receiver pair connections in the first and second USB connectors.

公开(公告)号：US20230102559A1

公开(公告)日：2023-03-30

申请号：US17448988

申请日：2021-09-27

Applicant: Dell Products L.P.

Inventor： Corey D. Hartman ,  Timothy M. Lambert ,  Isaac Q. Wang

IPC: G06F1/18 ,  G06F1/20 ,  H05K1/11

Abstract: In one embodiment, a method for distributing power using a power distribution system includes: receiving, by a first power distribution end of a power conductor of the power distribution system, power from a power supply unit via a first cable coupled to the power supply unit, the first power distribution end coupled to a first connector, the first connector including a first power interface coupling the first power distribution end to the first cable, the power conductor contoured to removably couple to a heatsink of the information handling system; and providing, by a second power distribution end of the power conductor, the power to a component of the information handling system via a second cable coupled to the component, the second power distribution end coupled to a second connector, the second connector including a second power interface coupling the second power distribution end to the second cable.

公开(公告)号：US11604756B1

公开(公告)日：2023-03-14

申请号：US17502303

申请日：2021-10-15

Applicant: Dell Products, L.P.

Inventor： Timothy M. Lambert ,  Marshal F. Savage ,  Robert T. Stevens

IPC: G06F13/42

Abstract: Embodiments of systems and methods for high-speed Out-of-Band (OOB) management links for inter-Baseboard Management Controller (BMC) communications in High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include: a system BMC; and an accelerator tray comprising: (a) one or more managed subsystems, (b) a tray BMC coupled to the one or more managed subsystems, and (c) a Field-Programmable Gate Array (FPGA) coupled to the tray BMC and to the system BMC.

公开(公告)号：US20230026653A1

公开(公告)日：2023-01-26

申请号：US17443125

申请日：2021-07-21

Applicant: Dell Products L.P.

Inventor： Timothy M. Lambert ,  Bhyrav Murthy Mutnury ,  Sandor Farkas

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/40

Abstract: An apparatus includes an interface with a plurality of channels; a multiplexer coupled to the interface and configured to couple transmit circuitry to a first channel mapped as a transmit path in a channel configuration and to couple receive circuitry to a second channel mapped as a receive path in the channel configuration; and a controller coupled to the multiplexer. The controller may be configured to perform the steps including determining a figure of merit of at least one channel of the plurality of channels of the interface; determining the channel configuration mapping transmit and receive paths to the plurality of the channels of the interface; and controlling the multiplexer to couple transmit circuitry to the first channel mapped as a transmit path in the channel configuration and to couple receive circuitry to the second channel mapped as a receive path in the channel configuration for dynamic channel swap(s).

公开(公告)号：US20220398105A1

公开(公告)日：2022-12-15

申请号：US17346721

申请日：2021-06-14

Applicant: Dell Products, L.P.

Inventor： Timothy M. Lambert ,  Eugene David Cho ,  Akkiah Choudary Maddukuri ,  Chandrasekhar Mugunda ,  Arun Muthaiyan ,  Hasnain Shabbir ,  Alaric J. Silveira ,  Sreeram Veluthakkal

IPC: G06F9/4401 ,  G06F11/30 ,  G06F1/20

Abstract: An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes executable instructions for monitoring a parameter of one or more of the hardware devices of the IHS when a custom BMC firmware stack is executed on the BMC. The instructions that monitor the parameter are separate and distinct from the instructions of the custom BMC firmware stack. When the parameter exceeds a specified threshold, the instructions are further executed to control the BMC to perform one or more operations to remediate the excessive parameter.

公开(公告)号：US11409686B1

公开(公告)日：2022-08-09

申请号：US17154836

申请日：2021-01-21

Applicant: Dell Products L.P.

Inventor： Timothy M. Lambert ,  Jeffrey L. Kennedy ,  Nihit S. Bhavsar

IPC: G06F13/40 ,  G06F1/12 ,  G06F1/26 ,  G06F11/14 ,  G06F13/10 ,  G06F13/12

Abstract: An information handling system may include a motherboard and a floating paddle card. The motherboard may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The floating paddle card may be communicatively coupled to the motherboard and configured to serve as interface between one or more devices coupled to the floating paddle card and the logic device and the management controller, the floating paddle card comprising a microcontroller unit configured to, alone or in combination with other circuitry of the floating paddle card, divide management of the one or more devices between the motherboard and the floating paddle card.

公开(公告)号：US11349965B1

公开(公告)日：2022-05-31

申请号：US17124774

申请日：2020-12-17

Applicant: Dell Products L.P.

Inventor： Yuchen Xu ,  Timothy M. Lambert ,  Jeffrey L. Kennedy

IPC: H04L69/22 ,  H01B13/34 ,  H04L69/24

Abstract: A system may include a controller, an endpoint device, and a cable coupled between the controller and the endpoint device and comprising a communication wire for bidirectionally communicating signals between the controller and the endpoint device and a circuit formed as a part of the cable and communicatively coupled to the communication wire, the circuit having a microcontroller unit configured to communicate identifying information regarding the cable to the controller via the communication wire and without contention with the signals bidirectionally communicated between the controller and the endpoint device.

公开(公告)号：US11348620B1

公开(公告)日：2022-05-31

申请号：US17158482

申请日：2021-01-26

Applicant: Dell Products L.P.

Inventor： Timothy M. Lambert ,  Jordan Chin ,  Nihit S. Bhavsar

IPC: G11C5/14 ,  G06F11/30

Abstract: An information handling system may include a memory comprising a plurality of memory modules, each memory module comprising a plurality of memory chips, a host system comprising a host system processor configured to, during a boot of the information handling system, execute a basic input/output system of the information handling system configured to monitor for one or more faults of one or more memory modules of the plurality of memory modules, and control circuitry. The control circuitry may be configured to, in response to the one or more faults, determine if, all of one or more memory modules associated with a power control signal of such one or more memory modules have experienced faults, and if all of the one or more memory modules associated with the power control signal have experienced faults, de-assert the power control signal such that the one or more memory modules are de-energized.