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公开(公告)号：US06405305B1
公开(公告)日：2002-06-11
申请号：US09394024
申请日：1999-09-10
IPC分类号： G06F9302
CPC分类号： G06F9/30087 , G06F9/30043 , G06F9/30094 , G06F9/30101 , G06F9/30189 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.
摘要翻译： 具有浮点单元的微处理器被配置为在程序顺序上下文中快速执行浮点负载控制字（FLDCW）类型指令。 浮点单元被配置为在调度FLDCW类型指令之前调度比FLDCW类型指令更早的指令。 FLDCW型指令作为屏障，以防止在FLDCW类型指令之前执行FLDCW类型指令之后的程序顺序发生的指令。 指示符位可以用于简化指令调度，并且可以存储具有长执行周期的指令的浮点控制字的副本。 还公开了一种配置成在程序顺序上下文中快速执行FLDCW型指令的方法和计算机。
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2.发明授权公开(公告)号：US06442677B1
公开(公告)日：2002-08-27
申请号：US09329497
申请日：1999-06-10
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/3826
摘要： An apparatus and method for superforwarding load operands in a microprocessor are provided. An execution unit in a microprocessor is configured to receive a load instruction and a subsequent instruction. If the load instruction corresponds to a simple load instruction, a destination operand of the load instruction can be superforwarded to a subsequent instruction if the subsequent instruction specifies a source operand that depends on the destination operand of the load instruction. The subsequent instruction is not required to wait until a load instruction executes or completes and can be scheduled and/or executed prior to or at the same time as the load instruction. Consequently, latencies associated with operand dependencies may be reduced.
摘要翻译： 提供了一种用于在微处理器中超载负载操作数的装置和方法。 微处理器中的执行单元被配置为接收加载指令和后续指令。 如果加载指令对应于简单的加载指令，则如果后续指令指定依赖于加载指令的目的地操作数的源操作数，则加载指令的目标操作数可以被超前给后续指令。 后续指令不需要等待加载指令执行或完成，并且可以在加载指令之前或同时进行调度和/或执行。 因此，可以减少与操作数相关性相关联的延迟。
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3.发明授权Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria 有权根据标准优化多管道可执行和特定管道可执行指令的分配到执行管道公开(公告)号：US06370637B1
公开(公告)日：2002-04-09
申请号：US09370789
申请日：1999-08-05
IPC分类号： G06F938
CPC分类号： G06F9/30032 , G06F9/30192 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are not forced to execute in a particular type of execution pipe. For example, junk ops are multi-pipeline executable. A junk op is an instruction that is executed at an early stage of the floating point unit's pipeline (e.g., during register rename), but still passes through an execution pipeline for exception checking. Junk ops are not limited to a particular execution pipeline, but instead may pass through any of the microprocessor's execution pipelines in the floating point unit. Multi-pipeline executable instructions are allocated on a per-clock cycle basis using a number of different criteria. For example, the allocation may vary depending upon the number of multi-pipeline executable instructions received by the floating point unit in a single clock cycle.
摘要翻译： 公开了一种具有配置成有效地分配多流水线可执行指令的浮点单元的微处理器。 多管道可执行指令是不强制在特定类型执行管道中执行的指令。 例如，垃圾操作是多管道可执行的。 垃圾操作是在浮点单元的流水线的早期执行的指令（例如，在寄存器重命名期间），但是仍然通过用于异常检查的执行管线。 垃圾操作不限于特定的执行管道，而是可以通过浮点单元中的任何一个微处理器的执行流水线。 使用许多不同的标准，在每个时钟周期的基础上分配多流水线可执行指令。 例如，分配可以根据浮点单元在单个时钟周期中接收的多流水线可执行指令的数量而变化。
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4.发明授权Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit 有权通过将比较结果存储在浮点单元中的临时寄存器中，FCOMI后快速执行FCMOV公开(公告)号：US06393555B1
公开(公告)日：2002-05-21
申请号：US09370787
申请日：1999-08-05
IPC分类号： G06F930
CPC分类号： G06F9/30021 , G06F9/30094 , G06F9/30101 , G06F9/3842 , G06F9/3885
摘要： A microprocessor with a floating point unit configured to rapidly execute floating point compare (FCOMI) type instructions that are followed by floating point conditional move (FCMOV) type instructions is disclosed. FCOMI-type instructions, which normally store their results to integer status flag registers, are modified to store a copy of their results to a temporary register located within the floating point unit. If an FCMOV-type instruction is detected following an FCOMI-type instruction, then the FCMOV-type instruction's source for flag information is changed from the integer flag register to the temporary register. FCMOV-type instructions are thereby able to execute earlier because they need not wait for the integer flags to be read from the integer portion of the microprocessor. A computer system and method for rapidly executing FCOMI-type instructions followed by FCMOV-type instructions are also disclosed.
摘要翻译： 具有浮点单元的微处理器被配置为快速执行浮点比较（FCOMI）类型指令，其后面是浮点条件移动（FCMOV）类型指令。 通常将其结果存储到整数状态标志寄存器的FCOMI型指令进行修改，以将其结果的副本存储到位于浮点单元内的临时寄存器。 如果在FCOMI型指令之后检测到FCMOV型指令，则FCMOV型指令的标志信息源从整数标志寄存器改变为临时寄存器。 因此，FCMOV型指令能够早期执行，因为它们不需要等待从微处理器的整数部分读取整数标志。 还公开了一种用于快速执行FCOMI型指令的计算机系统和方法，随后是FCMOV型指令。
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5.发明授权Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction 失效如果第二类型指令消耗由第一类型指令产生的数据，则将寄存器数据从第一格式类型转换为第二格式类型
公开(公告)号：US6105129A
公开(公告)日：2000-08-15
申请号：US25233
申请日：1998-02-18
CPC分类号： G06F9/30181 , G06F9/30036 , G06F9/30112 , G06F9/30152 , G06F9/30185 , G06F9/384 , G06F9/3855 , G06F9/3861
摘要： A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are the floating point registers defined in the x86 architecture, and the data formats are the floating point data format and the multimedia data format. The registers actually implemented by the microprocessor for the floating point registers use an internal format for floating point data. Part of the internal format is a classification field which classifies the floating point data in the extended precision defined by the x86 microprocessor architecture. Additionally, a classification field encoding is reserved for multimedia data. As the microprocessor begins execution of each multimedia instruction, the classification information of the source operands is examined to determine if the data is either in the multimedia class, or in a floating point class in which the significand portion of the register is the same as the corresponding significand in extended precision. If so, the multimedia instruction executes normally. If not, the multimedia instruction is faulted. Similarly, as the microprocessor begins execution of each floating point instruction, the classification information of the source operands is examined. If the data is classified as multimedia, the floating point instruction is faulted. A microcode routine is used to reformat the data stored in at least the source registers of the faulting instruction into a format useable by the faulting instruction. Subsequently, the faulting instruction is re-executed.
摘要翻译： 微处理器包括一个或多个寄存器，其被架构地定义为用于至少两种数据格式。 在一个实施例中，寄存器是在x86架构中定义的浮点寄存器，数据格式是浮点数据格式和多媒体数据格式。 微处理器为浮点寄存器实际实现的寄存器使用浮点数据的内部格式。 内部格式的一部分是分类字段，它以由x86微处理器架构定义的扩展精度对浮点数据进行分类。 此外，分类字段编码被保留用于多媒体数据。 当微处理器开始执行每个多媒体指令时，检查源操作数的分类信息以确定数据是在多媒体类中还是在浮点类中，其中寄存器的有效部分与 相应的显着性在扩展精度。 如果是这样，多媒体指令正常执行。 如果不是，则多媒体指令发生故障。 类似地，当微处理器开始执行每个浮点指令时，检查源操作数的分类信息。 如果数据被分类为多媒体，则浮点指令发生故障。 微码程序用于将存储在故障指令的至少源寄存器中的数据重新格式化为故障指令可使用的格式。 随后，重新执行故障指令。
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公开(公告)号：US06425074B1
公开(公告)日：2002-07-23
申请号：US09393524
申请日：1999-09-10
IPC分类号： G06F9302
CPC分类号： G06F9/30021 , G06F9/30094 , G06F9/30101 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859
摘要： A microprocessor configured to rapidly execute floating point store status word (FSTSW) type instructions that are immediately preceded by floating point compare (FCOM) type instructions is disclosed. FCOM-type instructions are modified to store their results to an architectural floating point status word and a temporary destination register. If an FSTSW-type instruction is detected immediately following an FCOM-type instruction, then the FSTSW-type instruction is transformed into a special fast floating point store status word (FSTSWEF) instruction. Unlike the FSTSW-type instruction, which is serializing and negatively impacts performance, the FSTSWEF instruction is not serializing and allows execution to continue without undue serialization. A computer system and method for rapidly executing FSTSW instructions immediately preceded by FCOM-type instructions are also disclosed.
摘要翻译： 公开了一种被配置为快速执行浮点比较（FCOM）类型指令之前的浮点存储状态字（FSTSW）类型指令的微处理器。 修改FCOM类型的指令以将其结果存储到架构浮点状态字和临时目标寄存器。 如果在FCOM型指令之后立即检测到FSTSW型指令，则FSTSW型指令被转换为特殊的快速浮点存储状态字（FSTSWEF）指令。 与串行化和负面影响性能的FSTSW型指令不同，FSTSWEF指令不是序列化的，允许执行继续，而不会过多的序列化。 还公开了一种用于在紧接在FCOM型指令之前快速执行FSTSW指令的计算机系统和方法。
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公开(公告)号：US07916864B2
公开(公告)日：2011-03-29
申请号：US11350137
申请日：2006-02-08
申请人： Norbert Juffa
发明人： Norbert Juffa
CPC分类号： G06F21/72 , G06F9/30181 , G06F9/3879 , G06F2207/3824
摘要： A graphics processing unit is programmed to carry out cryptographic processing so that fast, effective cryptographic processing solutions can be provided without incurring additional hardware costs. The graphics processing unit can efficiently carry out cryptographic processing because it has an architecture that is configured to handle a large number of parallel processes. The cryptographic processing carried out on the graphics processing unit can be further improved by configuring the graphics processing unit to be capable of both floating point and integer operations.
摘要翻译： 图形处理单元被编程为执行加密处理，使得可以提供快速有效的加密处理解决方案而不产生额外的硬件成本。 图形处理单元可以有效地执行加密处理，因为它具有被配置为处理大量并行进程的体系结构。 通过将图形处理单元配置为能够进行浮点运算和整数运算，可以进一步提高在图形处理单元上执行的加密处理。
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8.发明授权Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors 有权基于硬件资源的协作线程数组（CTA）的映射结果用于在包括多个多处理器的计算系统中有效的矩阵乘法的矩阵瓦片公开(公告)号：US07506134B1
公开(公告)日：2009-03-17
申请号：US11454542
申请日：2006-06-16
申请人： Norbert Juffa , Radoslav Danilak
发明人： Norbert Juffa , Radoslav Danilak
IPC分类号： G06F9/46
CPC分类号： G06F9/5066 , G06F9/5038 , G06F2209/5017
摘要： The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts.
摘要翻译： 本发明使得能够对并行处理装置进行有效的矩阵乘法运算。 一个实施例是用于将CTA映射到用于矩阵乘法运算的矩阵瓦片的方法。 另一个实施例是用于将CTA映射到结果瓦片的第二种方法。 其他实施例是用于将CTA的各个线程映射到块的元素以用于结果瓦片计算，源瓦片复制操作以及源瓦片复制和转置操作的方法。 本发明有利地使结果矩阵元素可以使用在不同的流式多处理器上同时执行的多个CTA来逐个瓦片地计算，使得能够将源瓦片复制到本地存储器，以减少当计算一个 结果图块，并且启用来自全局存储器的合并的读取操作以及对本地存储器的写入操作，而没有存储体冲突。
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公开(公告)号：US06381625B2
公开(公告)日：2002-04-30
申请号：US09782474
申请日：2001-02-12
IPC分类号： G06F7552
CPC分类号： G06F7/53 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338 , G06F7/5443 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16 , G06F2207/3828
摘要： A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evaluate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.
摘要翻译： 公开了能够执行有符号和无符号标量和矢量乘法的乘法器。 乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。 可以计算乘数和被乘数操作数的有效符号，并用于根据布斯算法创建和选择多个部分乘积。 一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。 结果可能是有符号或无符号的，可能表示向量或标量。 当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。 乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。 最终产品可以分段输出，以便需要更少的总线。 可以通过添加舍入常数来对段进行舍入。 可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。 乘法器还可以被配置为执行迭代计算以评估操作数的恒定功率。 形成的中间产品可以在两个路径中进行圆化和归一化，然后压缩并存储以用于下一次迭代。 还可以添加调整常数以增加精确舍入结果的频率。
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10.发明授权Apparatus and method for using checking instructions in a floating-point execution unit 有权在浮点执行单元中使用检查指令的装置和方法公开(公告)号：US06247117B1
公开(公告)日：2001-06-12
申请号：US09265230
申请日：1999-03-08
申请人： Norbert Juffa
发明人： Norbert Juffa
IPC分类号： G06F1500
CPC分类号： G06F9/226 , G06F9/30014 , G06F9/30192
摘要： The use of checking instructions to detect special and exceptional cases of a defined data format in a microprocessor is disclosed. Generally speaking, a checking instruction is included with the microcode of floating-point instructions to detect special and exceptional cases of operand values for the floating-point instructions. A checking instruction is configured to set one or more flags in a flags register if it detects a special or exceptional case for an operand value. A checking instruction may also set the result or results of a floating-point instruction to a result value if a special or exceptional case is detected. In addition, a checking instruction may be configured to set one or more bits in status register if a special or exceptional case is detected. After a checking instruction completes execution, a subsequent microcode instruction can be executed to determine if one or more flags were set by the checking instruction. If one or more flags have been set by the checking instruction, the subsequent microcode instruction can branch to a non-sequential microcode instruction to handle the special or exceptional case detected by the checking instruction.
摘要翻译： 公开了使用检查指令来检测微处理器中定义的数据格式的特殊和异常情况。 一般来说，浮点指令的微码中包含检查指令，以检测浮点指令的操作数值的特殊情况和异常情况。 检查指令被配置为在标志寄存器中设置一个或多个标志，如果它检测到操作数值的特殊或异常情况。 如果检测到特殊或特殊情况，则检查指令还可以将浮点指令的结果或结果设置为结果值。 此外，如果检测到特殊或特殊情况，则检查指令可以被配置为在状态寄存器中设置一个或多个位。 在检查指令完成执行之后，可以执行随后的微代码指令以确定检查指令是否设置了一个或多个标志。 如果通过检查指令设置了一个或多个标志，则后续的微代码指令可以转移到非顺序的微代码指令，以处理由检查指令检测到的特殊或特殊情况。
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