公开(公告)号：US6105129A

公开(公告)日：2000-08-15

申请号：US25233

申请日：1998-02-18

申请人： Stephan G. Meier ,  Norbert Juffa ,  Michael D. Achenbach ,  Frederick D. Weber

发明人： Stephan G. Meier ,  Norbert Juffa ,  Michael D. Achenbach ,  Frederick D. Weber

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/302

CPC分类号： G06F9/30181 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30152 ,  G06F9/30185 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3861

摘要： A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are the floating point registers defined in the x86 architecture, and the data formats are the floating point data format and the multimedia data format. The registers actually implemented by the microprocessor for the floating point registers use an internal format for floating point data. Part of the internal format is a classification field which classifies the floating point data in the extended precision defined by the x86 microprocessor architecture. Additionally, a classification field encoding is reserved for multimedia data. As the microprocessor begins execution of each multimedia instruction, the classification information of the source operands is examined to determine if the data is either in the multimedia class, or in a floating point class in which the significand portion of the register is the same as the corresponding significand in extended precision. If so, the multimedia instruction executes normally. If not, the multimedia instruction is faulted. Similarly, as the microprocessor begins execution of each floating point instruction, the classification information of the source operands is examined. If the data is classified as multimedia, the floating point instruction is faulted. A microcode routine is used to reformat the data stored in at least the source registers of the faulting instruction into a format useable by the faulting instruction. Subsequently, the faulting instruction is re-executed.

摘要翻译： 微处理器包括一个或多个寄存器，其被架构地定义为用于至少两种数据格式。 在一个实施例中，寄存器是在x86架构中定义的浮点寄存器，数据格式是浮点数据格式和多媒体数据格式。 微处理器为浮点寄存器实际实现的寄存器使用浮点数据的内部格式。 内部格式的一部分是分类字段，它以由x86微处理器架构定义的扩展精度对浮点数据进行分类。 此外，分类字段编码被保留用于多媒体数据。 当微处理器开始执行每个多媒体指令时，检查源操作数的分类信息以确定数据是在多媒体类中还是在浮点类中，其中寄存器的有效部分与 相应的显着性在扩展精度。 如果是这样，多媒体指令正常执行。 如果不是，则多媒体指令发生故障。 类似地，当微处理器开始执行每个浮点指令时，检查源操作数的分类信息。 如果数据被分类为多媒体，则浮点指令发生故障。 微码程序用于将存储在故障指令的至少源寄存器中的数据重新格式化为故障指令可使用的格式。 随后，重新执行故障指令。

公开(公告)号：US20120023314A1

公开(公告)日：2012-01-26

申请号：US12840835

申请日：2010-07-21

申请人： Matthew M. Crum ,  Michael D. Achenbach ,  Betty A. McDaniel ,  Benjamin T. Sander

发明人： Matthew M. Crum ,  Michael D. Achenbach ,  Betty A. McDaniel ,  Benjamin T. Sander

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3826

摘要： A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior to a scheduling pipe stage. For each data dependency, a distance value is determined based on a number of instructions a younger dependent instruction is located from a corresponding older (in program order) instruction. When the younger dependent instruction is allocated an entry in a multi-cycle scheduler, this distance value may be used to locate an entry storing the older instruction in the scheduler. When the older instruction is picked for issue, the younger dependent instruction is marked as pre-picked. In an immediately subsequent clock cycle, the younger dependent instruction may be picked for issue, thereby reducing the latency of the multi-cycle scheduler.

摘要翻译： 一种用于减少处理器内的多周期调度器的等待时间的方法和机制。 处理器包括前端流水线，其在调度管道级之前确定指令之间的数据依赖性。 对于每个数据依赖性，基于较年轻的依赖指令从相应的较旧（在程序顺序）指令中定位的指令的数量来确定距离值。 当在多循环调度器中分配较年轻的依赖指令时，该距离值可以用于定位存储在调度器中的旧指令的条目。 当较老的指令被挑选出来时，年龄较大的指令被标记为预选。 在随后的时钟周期中，可以挑选较年轻的依赖指令以进行发布，从而减少多周期调度器的等待时间。