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    Method and apparatus for rounding in a multiplier
    3.
    发明授权
    Method and apparatus for rounding in a multiplier 有权
    在乘法器中舍入的方法和装置

    公开(公告)号：US06397238B2

    公开(公告)日：2002-05-28

    申请号：US09782475

    申请日：2001-02-12

    Applicant: Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

    Inventor： Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

    IPC: G06F752

    CPC classification number: G06F7/53 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F17/16 ,  G06F2207/3828

    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evaluate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.

    Abstract translation: 公开了能够执行有符号和无符号标量和矢量乘法的乘法器。 乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。 可以计算乘数和被乘数操作数的有效符号，并用于根据布斯算法创建和选择多个部分乘积。 一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。 结果可能是有符号或无符号的，可能表示向量或标量。 当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。 乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。 最终产品可以分段输出，以便需要更少的总线。 可以通过添加舍入常数来对段进行舍入。 可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。 乘法器还可以被配置为执行迭代计算以评估操作数的恒定功率。 形成的中间产品可以在两个路径中进行圆化和归一化，然后压缩并存储以用于下一次迭代。 还可以添加调整常数以增加精确舍入结果的频率。

    Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit
    4.
    发明授权
    Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit 有权
    通过将比较结果存储在浮点单元中的临时寄存器中，FCOMI后快速执行FCMOV

    公开(公告)号：US06393555B1

    公开(公告)日：2002-05-21

    申请号：US09370787

    申请日：1999-08-05

    Applicant: Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

    Inventor： Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

    IPC: G06F930

    CPC classification number: G06F9/30021 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3842 ,  G06F9/3885

    Abstract: A microprocessor with a floating point unit configured to rapidly execute floating point compare (FCOMI) type instructions that are followed by floating point conditional move (FCMOV) type instructions is disclosed. FCOMI-type instructions, which normally store their results to integer status flag registers, are modified to store a copy of their results to a temporary register located within the floating point unit. If an FCMOV-type instruction is detected following an FCOMI-type instruction, then the FCMOV-type instruction's source for flag information is changed from the integer flag register to the temporary register. FCMOV-type instructions are thereby able to execute earlier because they need not wait for the integer flags to be read from the integer portion of the microprocessor. A computer system and method for rapidly executing FCOMI-type instructions followed by FCMOV-type instructions are also disclosed.

    Abstract translation: 具有浮点单元的微处理器被配置为快速执行浮点比较（FCOMI）类型指令，其后面是浮点条件移动（FC​​MOV）类型指令。 通常将其结果存储到整数状态标志寄存器的FCOMI型指令进行修改，以将其结果的副本存储到位于浮点单元内的临时寄存器。 如果在FCOMI型指令之后检测到FCMOV型指令，则FCMOV型指令的标志信息源从整数标志寄存器改变为临时寄存器。 因此，FCMOV型指令能够早期执行，因为它们不需要等待从微处理器的整数部分读取整数标志。 还公开了一种用于快速执行FCOMI型指令的计算机系统和方法，随后是FCMOV型指令。

    System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot
    5.
    发明授权
    System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot 失效
    将一个操作数从固定寄存器时隙和另一个操作数从任何寄存器时隙路由到算术逻辑单元的系统和方法

    公开(公告)号：US6009505A

    公开(公告)日：1999-12-28

    申请号：US759046

    申请日：1996-12-02

    Applicant: John S. Thayer ,  Gary W. Thome ,  Brian E. Longhenry ,  John G. Favor ,  Frederick D. Weber

    Inventor： John S. Thayer ,  Gary W. Thome ,  Brian E. Longhenry ,  John G. Favor ,  Frederick D. Weber

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F17/16

    CPC classification number: G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3877

    Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU. The operand routing may provide another operand from any source register slot location for another input to each respective ALU.

    Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。 在一个实施例中，多个ALU可以从固定的源寄存器时隙位置接收一个操作数，其中固定时隙位置对于每个ALU可以是不同的。 操作数路由可以从任何源寄存器时隙位置提供另一个操作数，用于另一个输入到每个相应的ALU。

    System and method for conditionally moving an operand from a source register to a destination register
    6.
    发明授权
    System and method for conditionally moving an operand from a source register to a destination register 失效
    用于有条件地将操作数从源寄存器移动到目标寄存器的系统和方法

    公开(公告)号：US5909572A

    公开(公告)日：1999-06-01

    申请号：US759025

    申请日：1996-12-02

    Applicant: John S. Thayer ,  John G. Favor ,  Frederick D. Weber

    Inventor： John S. Thayer ,  John G. Favor ,  Frederick D. Weber

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F9/00

    CPC classification number: G06F9/30072 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

    Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

    Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地路由和组合在矢量ALU。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

    Locking mechanism override and disable for personal computer ROM access protection
    8.
    发明授权
    Locking mechanism override and disable for personal computer ROM access protection 失效
    锁定机制覆盖并禁用个人计算机ROM访问保护

    公开(公告)号：US07003676B1

    公开(公告)日：2006-02-21

    申请号：US09871084

    申请日：2001-05-30

    Applicant: Frederick D. Weber ,  Dale E. Gulick

    Inventor： Frederick D. Weber ,  Dale E. Gulick

    IPC: G06F11/30 ,  H04L9/00

    CPC classification number: G06F21/82 ,  G06F21/74 ,  G06F21/79

    Abstract: A method and system for overriding access locks on secure assets in a computer system. The system includes a processor and a device coupled to the processor. The device includes one or more sub-devices, one or more access locks, and an access lock override register that stores one or more access lock override bits, including a lock override bit. The one or more access locks are configured to prevent access to the one or more sub-devices when the one or more access locks are engaged. Access to the one or more sub-devices is not allowed when the lock override bit is set. The method includes requesting a memory transaction for one or more memory addresses and determining a lock status for the one or more memory addresses. The method also includes returning the lock status for the one or more memory addresses. The method may determine if the lock status for the one or more memory address can be changed. The method may change the lock status of the one or more memory addresses to allow the memory transaction.

    Abstract translation: 用于覆盖计算机系统中安全资产上的访问锁的方法和系统。 该系统包括处理器和耦合到处理器的设备。 该设备包括一个或多个子设备，一个或多个访问锁和存储一个或多个访问锁覆盖位的访问锁覆盖寄存器，其包括锁倍增位。 所述一个或多个访问锁被配置为当所述一个或多个访问锁定被接合时防止访问所述一个或多个子设备。 锁定倍率位置1时，不允许访问一个或多个子设备。 该方法包括为一个或多个存储器地址请求存储器事务并确定一个或多个存储器地址的锁定状态。 该方法还包括返回一个或多个存储器地址的锁定状态。 该方法可以确定一个或多个存储器地址的锁定状态是否可以改变。 该方法可以改变一个或多个存储器地址的锁定状态以允许存储器事务。

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