公开(公告)号：US5420980A

公开(公告)日：1995-05-30

申请号：US33090

申请日：1993-03-16

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393 ,  G06T15/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5251296A

公开(公告)日：1993-10-05

申请号：US494997

申请日：1990-03-16

申请人： Desi Rhoden ,  Byron A. Alcorn ,  Darel N. Emmot ,  Ronald D. Larson

发明人： Desi Rhoden ,  Byron A. Alcorn ,  Darel N. Emmot ,  Ronald D. Larson

IPC分类号： G06F12/06 ,  G06T1/60 ,  G06T15/80 ,  G09G5/39 ,  G06F15/20 ,  G06F15/00

CPC分类号： G09G5/39 ,  G06T15/80 ,  G09G2360/122

摘要： Methods and apparatus for rendering graphics primitives to display devices in a computer graphics frame buffer system are disclosed. The methods provide an array of addressable video random access memory (VRAM) chips associated to form the graphics frame buffer. The VRAMs in the frame buffer are addressed with coordinate pixel locations on the display device corresponding to locations of the graphics primitives on the display device. The frame buffer is accessed with a graphics rendered according to arbitrarily shaped tiles containing pixels such that the pixels within the tiles have potentially different VRAM addresses.

公开(公告)号：US5564009A

公开(公告)日：1996-10-08

申请号：US459913

申请日：1995-06-02

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393 ,  G06F12/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5572657A

公开(公告)日：1996-11-05

申请号：US353489

申请日：1994-12-09

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393 ,  G06F12/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于窗口相对渲染图形原语的硬件解决方案，块移动图形基元，传输大数据块以及消除流水线冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5224210A

公开(公告)日：1993-06-29

申请号：US900535

申请日：1992-06-18

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US07629979B2

公开(公告)日：2009-12-08

申请号：US10644215

申请日：2003-08-20

申请人： Darel N. Emmot ,  Byron A. Alcorn ,  Ronald D. Larson

发明人： Darel N. Emmot ,  Byron A. Alcorn ,  Ronald D. Larson

IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F12/02 ,  G06F13/14

CPC分类号： G06F13/28

摘要： A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.

摘要翻译： 系统和方法将来自单线程应用程序的信息通过多个I / O总线传送到计算子系统进行处理。 根据一个实施例，提供了一种方法，其将用于与计算机子系统进行通信的状态顺序信息分开，通过多个输入/输出总线将分区信息传送到子系统，并且分别处理在多个输入/输出总线中接收的信息 的输入/输出总线，没有首先对信息进行排序。

公开(公告)号：US5745118A

公开(公告)日：1998-04-28

申请号：US465846

申请日：1995-06-06

申请人： Byron A. Alcorn ,  Darel N. Emmot ,  Steven Paul Tucker

发明人： Byron A. Alcorn ,  Darel N. Emmot ,  Steven Paul Tucker

IPC分类号： G06T11/20 ,  G06T15/04 ,  G06T15/00

CPC分类号： G06T15/04

摘要： A method and apparatus for managing texture mapping data in a computer graphics system, the system including a host computer, primitive rendering hardware and a textured primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes textured primitives to be rendered by the system using corresponding texture mapping data to the primitive rendering hardware over the textured primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the textured primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the textured primitives to be rendered. When texture mapping data corresponding to one of the textured primitives to be rendered is stored in the host computer main memory but not within the local texture mapping memory, the texture mapping data corresponding to the one of the textured primitives is downloaded from the host computer main memory to the local texture mapping memory through a texture mapping data path that is separate from the textured primitive data path.

摘要翻译： 一种用于在计算机图形系统中管理纹理映射数据的方法和装置，所述系统包括主计算机，原始呈现硬件和在主计算机和原始呈现硬件之间延伸的纹理化原始数据路径。 主计算机通过纹理原始图案将由系统渲染，使用相应的纹理映射数据到纹理原始数据路径上的原始渲染硬件。 主计算机具有存储与要渲染的纹理图元相对应的纹理映射数据的主存储器。 原始呈现硬件包括本地纹理存储器，其在本地存储对应于要渲染的纹理图元中的至少一个的纹理映射数据。 当与要呈现的纹理基元之一相对应的纹理映射数据存储在主计算机主存储器中而不存在于本地纹理映射存储器内时，与主机计算机主体相对应的纹理映射数据 通过与纹理化原始数据路径分离的纹理映射数据路径到本地纹理映射存储器的存储器。

公开(公告)号：US06873331B2

公开(公告)日：2005-03-29

申请号：US10109829

申请日：2002-03-29

申请人： Darel N. Emmot ,  Byron A. Alcorn

发明人： Darel N. Emmot ,  Byron A. Alcorn

IPC分类号： G06F9/46 ,  G06T1/60 ,  G06F15/16

CPC分类号： G06F9/546 ,  G06T1/60

摘要： The present invention is broadly directed to a system of components defining a plurality of nodes and a random access memory (RAM) connected to each node. The system comprises at least one producer functional unit configured to perform a predetermined processing function resulting in the creation of at least one producer message, a communication mechanism configured to manage and control communication of messages with other nodes, at least one pointer that is configurable to point to a storage location within the RAM, and a message logic configured to interpret content of the at least one producer message, the message logic further configured to associate the producer message with a subset of the at least one pointers based upon the content of the at least one producer message, the message logic further configured to store the at least one producer message within the RAM at the locations indicated by the associated subset of at least one pointer.

摘要翻译： 本发明广泛地涉及定义多个节点的组件系统和连接到每个节点的随机存取存储器（RAM）。 该系统包括至少一个生产者功能单元，其被配置为执行预定的处理功能，从而产生至少一个生产者消息，通信机制，被配置为管理和控制与其他节点的消息通信，至少一个指针，其可配置为 指向RAM内的存储位置，以及消息逻辑，其被配置为解释所述至少一个生成器消息的内容，所述消息逻辑还被配置为基于所述至少一个生成器消息的内容将所述生成器消息与所述至少一个指针的子集相关联 至少一个生成器消息，所述消息逻辑还被配置为在由至少一个指针的相关联的子集指示的位置处在所述RAM内存储所述至少一个生成器消息。

公开(公告)号：US06389504B1

公开(公告)日：2002-05-14

申请号：US09661094

申请日：2000-09-13

申请人： Steven P. Tucker ,  Byron A. Alcorn ,  Darel N. Emmot

发明人： Steven P. Tucker ,  Byron A. Alcorn ,  Darel N. Emmot

IPC分类号： G06F1208

CPC分类号： G06T1/60 ,  G06F12/0864 ,  G06F12/0875 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121

摘要： A method and apparatus for managing blocks of data in a data processing system, the data processing system including a host computer and data processing hardware, the host computer having a main memory that stores blocks of data to be processed by the data processing hardware, the data processing hardware including a local memory that locally stores a subset of the blocks of data to be processed by the data processing hardware. When a portion of one of the blocks of data is to be processed by the data processing hardware, a determination is made as to whether the block of data is in the local memory. When the block of data is in the local memory, the portion of the block of data to be processed is read from the local memory. When the block of data is not in the local memory, it is downloaded from the host computer main memory to the data processing hardware. The data processing hardware may generate an interrupt to the host computer with a request to download data.

摘要翻译： 一种用于管理数据处理系统中的数据块的方法和装置，所述数据处理系统包括主计算机和数据处理硬件，所述主计算机具有存储由数据处理硬件处理的数据块的主存储器， 数据处理硬件包括本地存储器，其本地存储要由数据处理硬件处理的数据块的子集。 当要由数据处理硬件处理其中一个数据块的一部分时，确定数据块是否在本地存储器中。 当数据块在本地存储器中时，将从本地存储器读取要处理的数据块的部分。 当数据块不在本地存储器中时，它从主计算机主存储器下载到数据处理硬件。 数据处理硬件可以通过下载数据的请求向主计算机产生中断。

公开(公告)号：US06919894B2

公开(公告)日：2005-07-19

申请号：US10624576

申请日：2003-07-21

申请人： Darel N. Emmot ,  Byron A. Alcorn

发明人： Darel N. Emmot ,  Byron A. Alcorn

IPC分类号： G06F15/173 ,  G06F15/17 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36 ,  G09G5/393 ,  G06F15/16

CPC分类号： G09G5/363 ,  G06F2209/509 ,  G09G5/393 ,  G09G2360/12 ,  G09G2360/125

摘要： A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

摘要翻译： 描述了广泛地涉及集成电路部件的系统的系统。 该系统包括通过通信链路互连的多个节点。 随机存取存储器（RAM）连接到每个节点。 至少一个功能单元集成到每个节点中，并且每个功能单元被配置为执行预定的处理功能。 最后，每个RAM包括被配置为仅允许其他节点对RAM的读取访问的一致性机制，所述一致性机制进一步被配置为仅允许通过对该节点本地的功能单元对RAM进行写访问。