公开(公告)号：US5564009A

公开(公告)日：1996-10-08

申请号：US459913

申请日：1995-06-02

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393 ,  G06F12/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5420980A

公开(公告)日：1995-05-30

申请号：US33090

申请日：1993-03-16

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393 ,  G06T15/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5251296A

公开(公告)日：1993-10-05

申请号：US494997

申请日：1990-03-16

申请人： Desi Rhoden ,  Byron A. Alcorn ,  Darel N. Emmot ,  Ronald D. Larson

发明人： Desi Rhoden ,  Byron A. Alcorn ,  Darel N. Emmot ,  Ronald D. Larson

IPC分类号： G06F12/06 ,  G06T1/60 ,  G06T15/80 ,  G09G5/39 ,  G06F15/20 ,  G06F15/00

CPC分类号： G09G5/39 ,  G06T15/80 ,  G09G2360/122

摘要： Methods and apparatus for rendering graphics primitives to display devices in a computer graphics frame buffer system are disclosed. The methods provide an array of addressable video random access memory (VRAM) chips associated to form the graphics frame buffer. The VRAMs in the frame buffer are addressed with coordinate pixel locations on the display device corresponding to locations of the graphics primitives on the display device. The frame buffer is accessed with a graphics rendered according to arbitrarily shaped tiles containing pixels such that the pixels within the tiles have potentially different VRAM addresses.

公开(公告)号：US5572657A

公开(公告)日：1996-11-05

申请号：US353489

申请日：1994-12-09

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393 ,  G06F12/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于窗口相对渲染图形原语的硬件解决方案，块移动图形基元，传输大数据块以及消除流水线冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5224210A

公开(公告)日：1993-06-29

申请号：US900535

申请日：1992-06-18

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5233689A

公开(公告)日：1993-08-03

申请号：US494701

申请日：1990-03-16

申请人： Desi Rhoden ,  Darel N. Emmot

发明人： Desi Rhoden ,  Darel N. Emmot

IPC分类号： G09G5/00 ,  G06T1/60 ,  G06T11/00 ,  G09G5/39

CPC分类号： G09G5/39

摘要： Methods and apparatus for maximizing column address coherency for serial and parallel port accesses to a dual port frame buffer. Performance of the serial port of the frame buffer is greatly improved by separating the page boundaries in the horizontal direction (i.e., scan line organized), while performance of the parallel port of the frame buffer is enhanced by organizing the page boundaries for rectangular areas of the display. Performance at both ports may be maximized at the same time by organizing the video random access memory (VRAM) into tiles and vertically barrel shifting the scan line data at a fixed interval across the video display. During operation, the serial port output looks like an entire row of data while it has actually output parts of N rows of data from two separate rows of memory chips which are changed at the fixed interval. This approach allows the parallel port to organize columns N times higher in the vertical direction. As a result, the page boundaries are N times as far apart in the vertical direction, thereby improving output performance.

公开(公告)号：US5457482A

公开(公告)日：1995-10-10

申请号：US254449

申请日：1994-06-06

申请人： Desi Rhoden ,  Darel N. Emmot

发明人： Desi Rhoden ,  Darel N. Emmot

IPC分类号： G09G5/39 ,  G09G5/393 ,  G09G1/02

CPC分类号： G09G5/39 ,  G09G2352/00 ,  G09G2360/121 ,  G09G5/393

摘要： A method and apparatus for the storage and retrieval of pixel information, including first and second data portions, is shown to include first and second memory devices each having a random access memory and a shift register, wherein the random access memory includes an on screen section and an off screen section. Pixel information is retrieved from the random access memories in response to control signals and transferred to the shift registers. A controller controls the storage and retrieval of the first data portion in the on screen section of the first memory device, controls the storage and retrieval of the second data portion in the off screen section of the second memory device and generates the control signals so that the first and second data portions are outputted from the shift registers simultaneously.

摘要翻译： 示出了包括第一和第二数据部分的用于存储和检索像素信息的方法和装置，其包括每个具有随机存取存储器和移位寄存器的第一和第二存储器件，其中随机存取存储器包括屏幕上部分 和截屏部分。 响应于控制信号从随机存取存储器中检索像素信息并传送到移位寄存器。 控制器控制第一存储装置的屏幕部分中的第一数据部分的存储和检索，控制第二存储装置的截屏部分中的第二数据部分的存储和检索，并产生控制信号，使得 第一和第二数据部分同时从移位寄存器输出。

公开(公告)号：US08060675B2

公开(公告)日：2011-11-15

申请号：US12644511

申请日：2009-12-22

申请人： Frank Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

发明人： Frank Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

IPC分类号： G06F13/00

CPC分类号： G06F13/1673 ,  G06F1/1632 ,  G06F13/1642 ,  G06F13/4013 ,  G06F13/4045 ,  G06F13/4282

摘要： A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

摘要翻译： 计算模块包括异步地与包括计算模块的计算机系统的一个或多个其他模块串行交换并行系统总线数据的接口。 计算模块可以异步地将第一并行总线数据串行地传送到计算机系统的另一模块，并且可以异步地从计算机系统的另一个模块串行接收第二并行总线数据。

公开(公告)号：US20060288141A1

公开(公告)日：2006-12-21

申请号：US11513806

申请日：2006-08-31

申请人： Frank Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

发明人： Frank Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

IPC分类号： G06F13/00

CPC分类号： G06F13/4045

摘要： A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention. The processor module can be upgraded to change or improve the performance of the modular computer system 20 without requiring any changes to the remaining system, thus drastically improving the price to performance trade-offs of the system. Moreover, the operating system (OS) of each module, including both the software and hardware, do not need to be changed as the entire modular system (20) is based on a common architecture, such as the PCI or Cardbus bus architecture.

摘要翻译： 一种模块化计算机系统（20），包括通过多个相应的高速串行链路（26,26）互连到多个远程模块（30,32,34,36,38,42）的通用连接站（UCS）（22） 40），例如基于专有的Split-Bridge（TM）技术。 包括可包括CPU，存储器，AGP图形和系统总线接口的核心部分的处理器模块（42）可以远程位于包括UCS（22）的其它模块中的每一个。 本发明实现了技术优点，其中模块化计算机系统（20）的每个模块出现在每个设备上，由于高速串行链路看起来是透明的，因此在并行总线上彼此互连。 优选地，虽然不是必需的，但是包括UCS 22的每个模块都基于PCI总线架构或PCMCIA总线架构，尽管其他总线架构非常适合于使用本发明来引入。 可以升级处理器模块以改变或改进模块化计算机系统20的性能，而不需要对剩余系统进行任何改变，从而大大提高系统的价格与性能的权衡。 此外，由于整个模块化系统（20）基于诸如PCI或Cardbus总线架构的通用架构，因此不需要改变每个模块的操作系统（OS），包括软件和硬件两者。

公开(公告)号：US20100100650A1

公开(公告)日：2010-04-22

申请号：US12644511

申请日：2009-12-22

申请人： Frank W. Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

发明人： Frank W. Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

IPC分类号： G06F13/38

CPC分类号： G06F13/1673 ,  G06F1/1632 ,  G06F13/1642 ,  G06F13/4013 ,  G06F13/4045 ,  G06F13/4282

摘要： A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

摘要翻译： 计算模块包括异步地与包括计算模块的计算机系统的一个或多个其他模块串行交换并行系统总线数据的接口。 计算模块可以异步地将第一并行总线数据串行地传送到计算机系统的另一模块，并且可以异步地从计算机系统的另一模块串行地接收第二并行总线数据。