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公开(公告)号：US09696923B2
公开(公告)日：2017-07-04
申请号：US14813097
申请日：2015-07-29
申请人： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng
发明人： Dimin Niu , Mu-Tien Chang , Hongzhong Zheng
CPC分类号： G06F3/0619 , G06F3/0659 , G06F3/0688 , G06F11/1048 , G06F11/1076 , G06F12/02 , G11C5/025 , G11C5/04 , G11C5/14
摘要： A memory module (735) can include a memory array (105) and a memory controller (740). The memory controller (740) can include a status register (745) that specifies whether the memory module (735) is operating at normal power or low power. A normal reliability region (305, 505) and a low reliability region (310, 510) can be defined in the memory array (105), based on the power level specified by the status register (745).
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公开(公告)号：US10013212B2
公开(公告)日：2018-07-03
申请号：US15086010
申请日：2016-03-30
申请人： Hongzhong Zheng , Mu-Tien Chang
发明人： Hongzhong Zheng , Mu-Tien Chang
IPC分类号： G06F3/06 , G06F12/08 , G06F12/10 , G06F9/455 , G06F12/0802 , G06F12/1009
CPC分类号： G06F3/0665 , G06F3/0613 , G06F3/0689 , G06F9/45558 , G06F12/0802 , G06F12/1009 , G06F2009/45583 , G06F2212/1024 , G06F2212/152 , G06F2212/621
摘要： An accelerator controller comprises a detector and a loader. The detector detects runtime features of an application or a virtual machine and identifies an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features. The loader loads the identified accelerator logic into at least one dynamic random access memory (DRAM). The at least one DRAM array is selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array based on the identified accelerator logic, and the at least one DRAM array is in a cache-coherent address space of the operating system environment. The accelerator logic may comprise a look-up table (LUT).
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公开(公告)号：US08072818B2
公开(公告)日：2011-12-06
申请号：US12654730
申请日：2009-12-30
申请人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
发明人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
CPC分类号： G11C8/16 , G11C11/412
摘要： The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.
摘要翻译： 本发明涉及双阈值电压双端口子阈值SRAM单元装置。 上述装置包括第一反相器，第二反相器，存取晶体管和读缓冲器。 第一反相器和第二反相器包括用于存储数据的多个第一操作元件和多个第二操作元件。 存取晶体管耦合到第一反相器和第二反相器，其中第一操作元件和第二操作元件是高阈值电压操作元件，并且存取晶体管是低阈值电压操作晶体管。 读缓冲器用于执行读操作。
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公开(公告)号：US20100172194A1
公开(公告)日：2010-07-08
申请号：US12654730
申请日：2009-12-30
申请人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
发明人： Mu-Tien Chang , Po-Tsang Huang , Wei Hwang
CPC分类号： G11C8/16 , G11C11/412
摘要： The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.
摘要翻译： 本发明涉及双阈值电压双端口子阈值SRAM单元装置。 上述装置包括第一反相器，第二反相器，存取晶体管和读缓冲器。 第一反相器和第二反相器包括用于存储数据的多个第一操作元件和多个第二操作元件。 存取晶体管耦合到第一反相器和第二反相器，其中第一操作元件和第二操作元件是高阈值电压操作元件，并且存取晶体管是低阈值电压操作晶体管。 读缓冲器用于执行读操作。
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