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1.发明授权公开(公告)号：US10567847B2
公开(公告)日：2020-02-18
申请号：US15290944
申请日：2016-10-11
IPC分类号： H04N21/234 , H04N21/643 , H04N21/434 , H04N21/6437 , H04N21/6405 , H04N21/435
摘要： There is provided a device comprising a non-transitory memory storing an executable code, a hardware processor executing the executable code to receive Internet protocol (IP) packets encapsulating a video content, the IP packets including a frame having a header storing header information relating to the video content, retrieve at least one portion of the header information relating to the video content from the header, retrieve the video content from the IP packets, prepare the retrieved video content for transmission using serial digital interface (SDI) protocol, insert the at least one portion of the header information into at least one of a vertical ancillary (VANC) data space and a horizontal ancillary (HANC) data space of the prepared video content using the SDI protocol, and transmit the prepared video content using the SDI protocol, including the at least one portion of the header information in the VANC space.
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公开(公告)号：US10541933B2
公开(公告)日：2020-01-21
申请号：US15348882
申请日：2016-11-10
IPC分类号： H04N21/43 , H04N21/643 , H04N21/845 , H04L12/873 , H04N21/44 , H04J3/06
摘要： There is provided a system including a non-transitory memory storing an executable code, and a hardware processor configured to execute the executable code to receive first and second Internet protocol (IP) video packets including respective first and second video content, and to identify a common reference time for the first and second IP video packets. The hardware processor also determines a first buffering interval for synchronizing the first and second IP video packets based on a first frame number, a first line number, and a first pixel number of the first video content, and the common reference time. In addition, the hardware processor holds the first IP video packet during the first buffering interval, and releases the first IP video packet when the first buffering interval elapses so as to align the first video content with the second video content at the common reference time.
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公开(公告)号：US20180270518A1
公开(公告)日：2018-09-20
申请号：US15462503
申请日：2017-03-17
IPC分类号： H04N21/24 , H04N21/61 , H04N21/218 , H04N21/854 , H04N21/2665
CPC分类号： H04N21/2407 , H04N5/262 , H04N5/2624 , H04N5/268 , H04N21/21805 , H04N21/23614 , H04N21/2665 , H04N21/6175 , H04N21/64322 , H04N21/84
摘要： According to one implementation, a tally management system includes a computing platform having a hardware processor and a system memory storing a tally management software code. The hardware processor executes the tally management software code to receive video production data identifying multiple video signals, and to map the video signals to corresponding video feed monitors for displaying the video signals. In addition, the hardware processor executes the tally management software code to receive selection data via a packet-switched network, the selection data identifying a primary monitor for displaying a video presentation, wherein a subset of the video signals contribute to the video presentation. The hardware processor further executes the tally management software to generate tally data identifying each of the video feed monitors corresponding respectively to the subset of video signals contributing to the video presentation, and to transmit the tally data via the packet-switched network.
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公开(公告)号：US20180131845A1
公开(公告)日：2018-05-10
申请号：US15348882
申请日：2016-11-10
IPC分类号： H04N5/04 , H04L12/873
CPC分类号： H04L47/522 , H04J3/0667 , H04N21/4302 , H04N21/44004 , H04N21/64322 , H04N21/8458
摘要： There is provided a system including a non-transitory memory storing an executable code, and a hardware processor configured to execute the executable code to receive first and second Internet protocol (IP) video packets including respective first and second video content, and to identify a common reference time for the first and second IP video packets. The hardware processor also determines a first buffering interval for synchronizing the first and second IP video packets based on a first frame number, a first line number, and a first pixel number of the first video content, and the common reference time. In addition, the hardware processor holds the first IP video packet during the first buffering interval, and releases the first IP video packet when the first buffering interval elapses so as to align the first video content with the second video content at the common reference time.
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公开(公告)号：US10250926B2
公开(公告)日：2019-04-02
申请号：US15462503
申请日：2017-03-17
IPC分类号： H04N21/24 , H04N21/61 , H04N21/2665 , H04N21/218 , H04N21/236 , H04N21/643 , H04N21/84 , H04N5/262 , H04N5/268
摘要： According to one implementation, a tally management system includes a computing platform having a hardware processor and a system memory storing a tally management software code. The hardware processor executes the tally management software code to receive video production data identifying multiple video signals, and to map the video signals to corresponding video feed monitors for displaying the video signals. In addition, the hardware processor executes the tally management software code to receive selection data via a packet-switched network, the selection data identifying a primary monitor for displaying a video presentation, wherein a subset of the video signals contribute to the video presentation. The hardware processor further executes the tally management software to generate tally data identifying each of the video feed monitors corresponding respectively to the subset of video signals contributing to the video presentation, and to transmit the tally data via the packet-switched network.
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6.发明申请公开(公告)号：US20180234474A1
公开(公告)日：2018-08-16
申请号：US15430861
申请日：2017-02-13
IPC分类号： H04L29/06 , H04N21/643 , H04N21/6332 , H04N21/6587
CPC分类号： H04N21/6587 , H04L65/4076 , H04L65/605 , H04L65/608 , H04N21/4325 , H04N21/6332 , H04N21/64322 , H04N21/6437 , H04N21/6543
摘要： Systems and methods to provide video signals and control signals over an internet protocol (IP) communications network are presented herein. Video signals and control signals may be obtained via an IP communications network. The control signals may be associated with the video signals using synchronization source identifiers as described in IETF RFC 3550.
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7.发明申请公开(公告)号：US20180103301A1
公开(公告)日：2018-04-12
申请号：US15290944
申请日：2016-10-11
IPC分类号： H04N21/643 , H04N21/6437 , H04N21/43 , H04N21/6405 , H04N21/435
摘要： There is provided a device comprising a non-transitory memory storing an executable code, a hardware processor executing the executable code to receive Internet protocol (IP) packets encapsulating a video content, the IP packets including a frame having a header storing header information relating to the video content, retrieve at least one portion of the header information relating to the video content from the header, retrieve the video content from the IP packets, prepare the retrieved video content for transmission using serial digital interface (SDI) protocol, insert the at least one portion of the header information into at least one of a vertical ancillary (VANC) data space and a horizontal ancillary (HANC) data space of the prepared video content using the SDI protocol, and transmit the prepared video content using the SDI protocol, including the at least one portion of the header information in the VANC space.
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