公开(公告)号：US20170047343A1

公开(公告)日：2017-02-16

申请号：US15208669

申请日：2016-07-13

申请人： Dohyun LEE ,  Younghwan SON ,  Minyeong SONG ,  YOUNGWOO PARK ,  Jaeduk LEE

发明人： Dohyun LEE ,  Younghwan SON ,  Minyeong SONG ,  YOUNGWOO PARK ,  Jaeduk LEE

IPC分类号： H01L27/115 ,  G11C16/08 ,  G11C16/26 ,  H01L29/167 ,  G11C16/10

CPC分类号： H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/167

摘要： Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.

摘要翻译： 提供一种三维半导体存储器件，其包括在半导体衬底上的外围逻辑结构，包括外围逻辑电路和下部绝缘间隙填充层，外围逻辑结构上的水平半导体层，堆叠在水平半导体层上， 包括垂直堆叠在水平半导体层上的多个电极的堆叠和穿过堆叠并连接到水平半导体层的多个垂直结构。 水平半导体层可以包括设置在下绝缘间隙填充层上并与反扩散材料共掺杂的第一半导体层和第一杂质浓度的第一导电型杂质，以及设置在第一半导体层上的第二半导体层， 掺杂具有低于第一杂质浓度的第二杂质浓度的第一导电型杂质或未掺杂的。