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    Jelly-roll having active material layer with different loading amount
    1.
    发明授权
    Jelly-roll having active material layer with different loading amount 有权
    果冻卷具有不同负载量的活性物质层

    公开(公告)号：US08129049B2

    公开(公告)日：2012-03-06

    申请号：US12532687

    申请日：2008-03-24

    申请人： Jong Hee Kim ,  Dongmyung Kim ,  Hyungook Yoon ,  Yong Jeong Kim ,  Joo-Hwan Sung ,  Seung W. Chu ,  Sung-Pil Yoon ,  Dohyun Lee

    发明人： Jong Hee Kim ,  Dongmyung Kim ,  Hyungook Yoon ,  Yong Jeong Kim ,  Joo-Hwan Sung ,  Seung W. Chu ,  Sung-Pil Yoon ,  Dohyun Lee

    IPC分类号： H01M4/00 ,  H01M4/13 ,  H01M6/48 ,  H01M10/18

    CPC分类号： H01M10/0431 ,  H01M10/0587

    摘要： Disclosed herein is a jelly-roll type electrode assembly (“jelly-roll”) of a cathode/separator/anode structure, wherein the jelly-roll is constructed in a structure in which each electrode has active material layers formed on opposite major surfaces of a sheet-type current collector, the loading amount of an active material for the inner active material layer, constituting the inner surface of each sheet when each sheet is wound, is less than that of an active material for the outer active material layer, constituting the outer surface of each sheet when each sheet is wound, and the loading amount of the active material for the inner active material layer gradually increases from the central region of each wound sheet to the outermost region of each wound sheet.

    摘要翻译： 本文公开了阴极/分离器/阳极结构的胶卷式电极组件（“胶卷”），其中胶卷被构造成其中每个电极具有形成在相对主表面上的活性材料层的结构 构成片材每个片材的内表面的构成内部活性物质层的活性物质的负载量小于外部活性物质层的活性物质的负载量，构成 每个片材被卷绕时的每个片材的外表面，并且用于内部活性材料层的活性材料的负载量从每个缠绕片材的中心区域逐渐增加到每个缠绕片材的最外部区域。

    Three-dimensional semiconductor devices with current path selection structure
    3.
    发明授权
    Three-dimensional semiconductor devices with current path selection structure 有权
    具有电流路径选择结构的三维半导体器件

    公开(公告)号：US09299707B2

    公开(公告)日：2016-03-29

    申请号：US14150452

    申请日：2014-01-08

    申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C16/14

    CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

    摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

    摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
    三维半导体存储器件

    公开(公告)号：US20170047343A1

    公开(公告)日：2017-02-16

    申请号：US15208669

    申请日：2016-07-13

    申请人： Dohyun LEE ,  Younghwan SON ,  Minyeong SONG ,  YOUNGWOO PARK ,  Jaeduk LEE

    发明人： Dohyun LEE ,  Younghwan SON ,  Minyeong SONG ,  YOUNGWOO PARK ,  Jaeduk LEE

    IPC分类号： H01L27/115 ,  G11C16/08 ,  G11C16/26 ,  H01L29/167 ,  G11C16/10

    CPC分类号： H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/167

    摘要： Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.

    摘要翻译： 提供一种三维半导体存储器件，其包括在半导体衬底上的外围逻辑结构，包括外围逻辑电路和下部绝缘间隙填充层，外围逻辑结构上的水平半导体层，堆叠在水平半导体层上， 包括垂直堆叠在水平半导体层上的多个电极的堆叠和穿过堆叠并连接到水平半导体层的多个垂直结构。 水平半导体层可以包括设置在下绝缘间隙填充层上并与反扩散材料共掺杂的第一半导体层和第一杂质浓度的第一导电型杂质，以及设置在第一半导体层上的第二半导体层， 掺杂具有低于第一杂质浓度的第二杂质浓度的第一导电型杂质或未掺杂的。

    JELLY-ROLL HAVING ACTIVE MATERIAL LAYER WITH DIFFERENT LOADING AMOUNT
    8.
    发明申请
    JELLY-ROLL HAVING ACTIVE MATERIAL LAYER WITH DIFFERENT LOADING AMOUNT 有权
    具有不同负载量的活性材料层的JELLY-ROLL

    公开(公告)号：US20100104930A1

    公开(公告)日：2010-04-29

    申请号：US12532687

    申请日：2008-03-24

    申请人： Jong Hee Kim ,  Dongmyung Kim ,  Hyungook Yoon ,  Yong Jeong Kim ,  Joo-Hwan Sung ,  Seung W. Chu ,  Sung-Pil Yoon ,  Dohyun Lee

    发明人： Jong Hee Kim ,  Dongmyung Kim ,  Hyungook Yoon ,  Yong Jeong Kim ,  Joo-Hwan Sung ,  Seung W. Chu ,  Sung-Pil Yoon ,  Dohyun Lee

    IPC分类号： H01M6/10

    CPC分类号： H01M10/0431 ,  H01M10/0587

    摘要： Disclosed herein is a jelly-roll type electrode assembly (“jelly-roll”) of a cathode/separator/anode structure, wherein the jelly-roll is constructed in a structure in which each electrode has active material layers formed on opposite major surfaces of a sheet-type current collector, the loading amount of an active material for the inner active material layer, constituting the inner surface of each sheet when each sheet is wound, is less than that of an active material for the outer active material layer, constituting the outer surface of each sheet when each sheet is wound, and the loading amount of the active material for the inner active material layer gradually increases from the central region of each wound sheet to the outermost region of each wound sheet.

    摘要翻译： 本文公开了阴极/分离器/阳极结构的胶卷式电极组件（“胶卷”），其中胶卷被构造成其中每个电极具有形成在相对主表面上的活性材料层的结构 构成片材每个片材的内表面的构成内部活性物质层的活性物质的负载量小于外部活性物质层的活性物质的负载量，构成 每个片材被卷绕时的每个片材的外表面，并且用于内部活性材料层的活性材料的负载量从每个缠绕片材的中心区域逐渐增加到每个缠绕片材的最外部区域。

    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE 有权
    具有互连结构的半导体器件

    公开(公告)号：US20170011996A1

    公开(公告)日：2017-01-12

    申请号：US15201922

    申请日：2016-07-05

    申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

    发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

    IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

    CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

    摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。