公开(公告)号：US20180197585A1

公开(公告)日：2018-07-12

申请号：US15866156

申请日：2018-01-09

Applicant: Dolphin Integration

Inventor： Julien Louche ,  Olivier Mercier ,  Khaja Ahmad Shaik

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/10 ,  G11C7/18 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419

Abstract: A memory circuit having: a control circuit of a line of a memory array including: a first transistor coupled between first and second nodes and controlled by a line selection signal including a high level and a low level; a second transistor controlled by a first signal and coupled between the first node and a voltage supply rail of a first supply voltage, the first supply voltage being higher than the high level of the line selection signal, the first node being coupled to a line of memory array, the second node receiving a timing signal; and a line deactivation circuit adapted to generate the first signal and including a reference cell and a level shifter.