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公开(公告)号：US20190227614A1
公开(公告)日：2019-07-25
申请号：US16337300
申请日：2017-09-26
Applicant: Dolphin Integration
Inventor： Emmanuel GRAND
IPC: G06F1/3234 , H03G3/30 , G10L25/78 , G10L15/28
Abstract: A circuit for sound activity detection includes a transducer adapted to generate an electrical signal based on detected sound; a variable gain amplifier adapted to amplify the electrical signal to generate an amplified electrical signal; a comparator adapted to compare the amplified electrical signal with at least one first threshold level to generate a comparison signal indicating comparator events; and a control circuit adapted to generate, based on the comparison signal, a gain control signal for controlling the gain of the variable gain amplifier, and a sound activity alert signal indicating the detection of sound activity.
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公开(公告)号：US20160099027A1
公开(公告)日：2016-04-07
申请号：US14871508
申请日：2015-09-30
Applicant: Dolphin Integration
Inventor： Oron Chertkow , Ariel Pescovsky
CPC classification number: G11C11/4125 , G11C5/005 , G11C14/00 , G11C16/0441 , G11C16/10 , G11C29/789
Abstract: The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).
Abstract translation: 本发明涉及一种存储器单元，其具有：第一和第二交叉耦合门控反相器（102,104），每个反相器包括第一和第二输入（IN1，IN2）和输出（OUT），并且适于将其输出耦合到第一逻辑 只有当第一和第二输入都接收到第一逻辑电平的反相时; 将第一选通逆变器（102）的第二输入（IN2）与第一选通逆变器（102）的第一输入（IN1）耦合的第一截止电路（106）; 以及将第二选通逆变器（104）的第二输入（IN2）与第二门控逆变器（104）的第一输入（IN1）耦合的第二截止电路（108）。
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公开(公告)号：US10908670B2
公开(公告)日：2021-02-02
申请号：US16337300
申请日：2017-09-26
Applicant: Dolphin Integration
Inventor： Emmanuel Grand
IPC: G10L15/20 , G06F1/3234 , G10L25/78 , G06F1/3206 , G06F1/3287 , H03G3/30 , H03G3/34 , G10L15/28 , G10L25/93 , G10L25/87
Abstract: A circuit for sound activity detection includes a transducer (106) adapted to generate an electrical signal based on detected sound; a variable gain amplifier adapted to amplify the electrical signal to generate an amplified electrical signal; a comparator adapted to compare the amplified electrical signal with at least one first threshold level to generate a comparison signal indicating comparator events; and a control circuit adapted to generate, based on the comparison signal, a gain control signal for controlling the gain of the variable gain amplifier, and a sound activity alert signal indicating the detection of sound activity.
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公开(公告)号：US10236000B2
公开(公告)日：2019-03-19
申请号：US15654153
申请日：2017-07-19
Applicant: DOLPHIN INTEGRATION
Inventor： Paul Giletti
Abstract: The invention concerns a circuit for speech recognition comprising: a voice detection circuit configured to detect, based on at least one input parameter, the presence of a voice signal in an input audio signal and to generate an activation signal on each voice detection event; a speech recognition circuit configured to be activated by the activation signal and to perform speech recognition on the input audio signal, the speech recognition circuit being further configured to generate an output signal indicating, based on the speech recognition, whether each voice detection event is true or false; and an analysis circuit configured to generate, based on the output signal of the speech recognition circuit, a control signal for modifying one or more of said input parameters.
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公开(公告)号：US20170228326A1
公开(公告)日：2017-08-10
申请号：US15425877
申请日：2017-02-06
Applicant: DOLPHIN INTEGRATION
Inventor： Gilles DEPEYROT , Olivier MONFORT
CPC classification number: G06F12/1425 , G06F9/3802 , G06F12/1408 , G06F21/6218 , G06F21/74 , G06F21/79 , G06F2212/402
Abstract: The present invention concerns a method of protecting sensitive data, and a corresponding computing system processing device, comprising: entering, by a processing device, a sensitive date access mode in-which sensitive data is accessible; restricting, by a program running in the sensitive data access mode, one or more accessible address ranges for a non-secure function, and calling, from the sensitive data access mode, the non-secure function; and entering, by the processing device, a further operating mode to execute the non-secure function during which the processing device has access to only the one or more accessible address ranges.
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Patent Agency Ranking
公开(公告)号：US09641134B2
公开(公告)日：2017-05-02
申请号：US14832910
申请日：2015-08-21
Applicant: Dolphin Integration
Inventor： Emmanuel Grand , Sébastien Genevey , Arthur Veith , Paul Giletti
CPC classification number: H03F1/26 , H03F1/305 , H03F3/185 , H03F3/45179 , H03F2200/03 , H03F2200/129
Abstract: The invention concerns an amplifier circuit comprising: an amplifier having a first input coupled to an input node of the amplifier circuit via a first resistor and an output coupled to a load via a coupling capacitor, the output being coupled to the first input via a second resistor; and a current ramp generator adapted to supply a current ramp to the first input of the amplifier during a power up phase or power down phase of the amplifier circuit to control the rate of charge or discharge of the coupling capacitor.
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公开(公告)号：US10223290B2
公开(公告)日：2019-03-05
申请号：US15425877
申请日：2017-02-06
Applicant: DOLPHIN INTEGRATION
Inventor： Gilles Depeyrot , Olivier Monfort
Abstract: The present invention concerns a method of protecting sensitive data, and a corresponding computing system processing device, comprising: entering, by a processing device, a sensitive date access mode in-which sensitive data is accessible; restricting, by a program running in the sensitive data access mode, one or more accessible address ranges for a non-secure function, and calling, from the sensitive data access mode, the non-secure function; and entering, by the processing device, a further operating mode to execute the non-secure function during which the processing device has access to only the one or more accessible address ranges.
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公开(公告)号：US20140184318A1
公开(公告)日：2014-07-03
申请号：US14141369
申请日：2013-12-26
Applicant: Dolphin Integration
Inventor： Loïc Sibeud , Grégoire Gimenez
IPC: G05F1/46
CPC classification number: G05F1/468 , H03K19/0016
Abstract: The invention concerns power supply circuitry for controlling a power-up phase of an islet of an integrated circuit, the circuitry having: a switch (102) controlled by a current and coupled between a supply voltage rail (104) and an internal voltage rail (105) of the islet.
Abstract translation: 本发明涉及用于控制集成电路的小岛的上电阶段的电源电路，该电路具有：由电流控制并耦合在电源电压轨道（104）和内部电压轨道（104）之间的开关（102） 105）的小岛。
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公开(公告)号：US20140104936A1
公开(公告)日：2014-04-17
申请号：US14051357
申请日：2013-10-10
Applicant: DOLPHIN INTEGRATION
Inventor： Ilan Sever
IPC: G11C11/412 , G11C29/08
CPC classification number: G11C11/412 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/22 , G11C11/418 , G11C11/419 , G11C29/08
Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.
Abstract translation: 本发明涉及具有以列和行排列的存储单元的存储器阵列，每列的存储单元耦合到其列的至少一个公共写入线，每行的存储单元耦合到其行的公共选择行 其中每个存储单元包括由在第一和第二存储节点之间交叉耦合的一对反相器形成的锁存器; 耦合在第一存储节点和第一测试数据输入之间的第一晶体管; 以及耦合在所述第二存储节点和第二测试数据输入之间的第二晶体管。
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公开(公告)号：US20180025730A1
公开(公告)日：2018-01-25
申请号：US15654153
申请日：2017-07-19
Applicant: DOLPHIN INTEGRATION
Inventor： Paul GILETTI
CPC classification number: G10L17/005 , G10L15/142 , G10L15/16 , G10L15/20 , G10L25/78 , G10L25/84 , G10L2015/025 , G10L2025/783 , G10L2025/786
Abstract: The invention concerns a circuit for speech recognition comprising: a voice detection circuit configured to detect, based on at least one input parameter, the presence of a voice signal in an input audio signal and to generate an activation signal on each voice detection event; a speech recognition circuit configured to be activated by the activation signal and to perform speech recognition on the input audio signal, the speech recognition circuit being further configured to generate an output signal indicating, based on the speech recognition, whether each voice detection event is true or false; and an analysis circuit configured to generate, based on the output signal of the speech recognition circuit, a control signal for modifying one or more of said input parameters.
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