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公开(公告)号：US08090928B2
公开(公告)日：2012-01-03
申请号：US10184402
申请日：2002-06-28
IPC分类号： G06F15/76
CPC分类号： G06F9/3887 , G06F9/30036 , G06F9/3877 , G06F9/3897 , G06F15/8076 , H04M2201/34
摘要： In one embodiment of the present invention, a processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, where the engines are adapted to minimize data exchange penalties by processing small in-out bit slices.
摘要翻译： 在本发明的一个实施例中，处理器包括标量计算单元; 耦合到标量计算单元的矢量协处理器; 以及耦合到标量计算单元的一个或多个功能特定引擎，其中引擎适于通过处理小的进出位片来最小化数据交换惩罚。
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2.发明授权Clocking system including a clock controller that uses buffer feedback to vary a clock frequency 有权时钟系统包括使用缓冲器反馈来改变时钟频率的时钟控制器公开(公告)号：US07398414B2
公开(公告)日：2008-07-08
申请号：US11240999
申请日：2005-09-29
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/329 , G06F9/3869 , H04W52/0293 , Y02D10/126 , Y02D10/24 , Y02D70/1224 , Y02D70/142 , Y02D70/144
摘要： A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.
摘要翻译： 低功率可重配置处理器核心包括一个或多个处理单元，每个单元具有控制单元性能的时钟输入; 一个或多个时钟控制器具有耦合到处理单元的时钟输入的时钟输出，控制器操作改变每个处理单元的时钟频率以优化任务的速度和处理能力; 以及耦合到处理单元的高密度存储器阵列芯。
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公开(公告)号：US07139921B2
公开(公告)日：2006-11-21
申请号：US10867901
申请日：2004-06-14
IPC分类号： G06F1/32
CPC分类号： G06F9/30101 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/30083 , G06F9/30094 , G06F9/3869 , G06F9/3885 , Y02D10/126 , Y02D10/172
摘要： A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to a respective clock input of one of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.
摘要翻译： 低功率可重配置处理器核心包括一个或多个处理单元，每个单元具有控制单元性能的时钟输入; 以及控制器，其具有多个时钟输出，每个时钟输出耦合到所述处理单元之一的相应时钟输入，所述控制器改变每个处理单元的时钟频率，以优化功率消耗和任务的处理能力。
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公开(公告)号：US06993669B2
公开(公告)日：2006-01-31
申请号：US09837651
申请日：2001-04-18
IPC分类号： G06F1/32
CPC分类号： G06F9/30101 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/30083 , G06F9/30094 , G06F9/3869 , G06F9/3885 , Y02D10/126 , Y02D10/172
摘要： A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.
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公开(公告)号：US06990598B2
公开(公告)日：2006-01-24
申请号：US09814355
申请日：2001-03-21
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/329 , G06F9/3869 , H04W52/0293 , Y02D10/126 , Y02D10/24 , Y02D70/1224 , Y02D70/142 , Y02D70/144
摘要： A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.
摘要翻译： 低功率可重配置处理器核心包括一个或多个处理单元，每个单元具有控制单元性能的时钟输入; 一个或多个时钟控制器具有耦合到处理单元的时钟输入的时钟输出，控制器操作改变每个处理单元的时钟频率以优化任务的速度和处理能力; 以及耦合到处理单元的高密度存储器阵列芯。
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