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公开(公告)号:US07502976B2
公开(公告)日:2009-03-10
申请号:US10779205
申请日:2004-02-13
申请人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
CPC分类号: G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译: 公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。 所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。 该示例性实施例包括输入逻辑,其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径,存储器内置自检(MBIST)控制器,以及耦合在输入逻辑和 MBIST控制器。 本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。 在存储器测试模式下,扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。 在诸如电子设计自动化(“EDA”)软件工具的计算机执行的应用中,可以设计,模拟和/或验证任何公开的装置(并且可以执行任何公开的方法)。
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公开(公告)号:US08209572B2
公开(公告)日:2012-06-26
申请号:US12941404
申请日:2010-11-08
申请人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
CPC分类号: G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译: 公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。 所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。 该示例性实施例包括输入逻辑,其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径,存储器内置自检(MBIST)控制器,以及耦合在输入逻辑和 MBIST控制器。 本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。 在存储器测试模式下,扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。 在诸如电子设计自动化(“EDA”)软件工具的计算机执行的应用中,可以设计,模拟和/或验证任何公开的装置(并且可以执行任何公开的方法)。
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公开(公告)号:US20090172486A1
公开(公告)日:2009-07-02
申请号:US12400664
申请日:2009-03-09
申请人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
IPC分类号: G01R31/3187 , G06F11/00
CPC分类号: G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译: 公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。 所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。 该示例性实施例包括输入逻辑,其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径,存储器内置自检(MBIST)控制器,以及耦合在输入逻辑和 MBIST控制器。 本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。 在存储器测试模式下,扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。 在诸如电子设计自动化(“EDA”)软件工具的计算机执行的应用中,可以设计,模拟和/或验证任何公开的装置(并且可以执行任何公开的方法)。
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公开(公告)号:US20110145774A1
公开(公告)日:2011-06-16
申请号:US12941404
申请日:2010-11-08
申请人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
IPC分类号: G06F17/50
CPC分类号: G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译: 公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。 所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。 该示例性实施例包括输入逻辑,其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径,存储器内置自检(MBIST)控制器,以及耦合在输入逻辑和 MBIST控制器。 本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。 在存储器测试模式下,扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。 在诸如电子设计自动化(“EDA”)软件工具的计算机执行的应用中,可以设计,模拟和/或验证任何公开的装置(并且可以执行任何公开的方法)。
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公开(公告)号:US07831871B2
公开(公告)日:2010-11-09
申请号:US12400664
申请日:2009-03-09
申请人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人: Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
CPC分类号: G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译: 公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。 所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。 该示例性实施例包括输入逻辑,其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径,存储器内置自检(MBIST)控制器,以及耦合在输入逻辑和 MBIST控制器。 本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。 在存储器测试模式下,扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。 在诸如电子设计自动化(“EDA”)软件工具的计算机执行的应用中,可以设计,模拟和/或验证任何公开的装置(并且可以执行任何公开的方法)。
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6.
公开(公告)号:US07434131B2
公开(公告)日:2008-10-07
申请号:US11282938
申请日:2005-11-18
申请人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号: G01R31/28
CPC分类号: G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译: 公开了可编程存储器内置的自检(MBIST)方法,装置和系统。 所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。
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公开(公告)号:US07426668B2
公开(公告)日:2008-09-16
申请号:US11283499
申请日:2005-11-18
申请人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号: G01R31/28
CPC分类号: G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译: 公开了可编程存储器内置的自检(MBIST)方法,装置和系统。 所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。
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公开(公告)号:US07200786B2
公开(公告)日:2007-04-03
申请号:US10749283
申请日:2003-12-30
申请人: Wu-Tung Cheng , Joseph Rayhawk , Xiaogang Du
发明人: Wu-Tung Cheng , Joseph Rayhawk , Xiaogang Du
CPC分类号: G11C29/4401 , G11C29/44 , G11C2029/0401
摘要: Methods and apparatus for analyzing memory defects in an embedded memory are described. According to certain embodiments, the analysis can be performed “at-speed” and can be used to analyze multi-bit failures in words of a word-oriented memory. According to some embodiments, the analysis comprises updating a record of column defects not repaired by spare rows as the memory is being tested. The record can be evaluated after a test to determine whether a repair strategy can successfully repair a memory-under-test.
摘要翻译: 描述了用于分析嵌入式存储器中的存储器缺陷的方法和装置。 根据某些实施例,可以“速度”地执行分析,并且可以用于分析面向字的存储器的单词中的多位故障。 根据一些实施例,分析包括当正在测试存储器时更新未被备用行修复的列缺陷的记录。 测试后可以评估该记录,以确定修复策略是否可以成功修复被测内存。
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9.
公开(公告)号:US20060156134A1
公开(公告)日:2006-07-13
申请号:US11283527
申请日:2005-11-18
申请人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号: G01R31/28
CPC分类号: G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译: 公开了可编程存储器内置的自检(MBIST)方法,装置和系统。 所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。
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10.
公开(公告)号:US20060156133A1
公开(公告)日:2006-07-13
申请号:US11282938
申请日:2005-11-18
申请人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人: Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号: G01R31/28
CPC分类号: G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译: 公开了可编程存储器内置的自检(MBIST)方法,装置和系统。 所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。
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