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102 条记录 (耗时 0.029 秒)

    Reduced-pin-count-testing architectures for applying test patterns
    7.
    发明授权
    Reduced-pin-count-testing architectures for applying test patterns 有权
    用于应用测试模式的减少针数测试架构

    公开(公告)号：US07487419B2

    公开(公告)日：2009-02-03

    申请号：US11305849

    申请日：2005-12-16

    申请人： Nilanjan Mukherjee ,  Jay Jahangiri ,  Ronald Press ,  Wu-Tung Cheng

    发明人： Nilanjan Mukherjee ,  Jay Jahangiri ,  Ronald Press ,  Wu-Tung Cheng

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541 ,  G01R31/318572 ,  G01R31/318583

    摘要： Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.

    摘要翻译： 公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。 方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。 例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。 电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。 在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到对应于用于控制电路的一个或多个内部扫描链的测试控制信号的一个或多个边界扫描单元 测试中测试。 该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。

    Scheduling the concurrent testing of multiple cores embedded in an integrated circuit
    8.
    发明授权
    Scheduling the concurrent testing of multiple cores embedded in an integrated circuit 有权
    调度嵌入在集成电路中的多个内核的并发测试

    公开(公告)号：US06934897B2

    公开(公告)日：2005-08-23

    申请号：US10210794

    申请日：2002-07-31

    申请人： Nilanjan Mukherjee ,  Chien-Chung Tsai ,  Wu-Tung Cheng ,  Omer Ghazi Samman ,  Yahya M. Z. Mustafa ,  Paul J. Reuter ,  Yu Huang ,  Sudhakar Mannapuram Reddy

    发明人： Nilanjan Mukherjee ,  Chien-Chung Tsai ,  Wu-Tung Cheng ,  Omer Ghazi Samman ,  Yahya M. Z. Mustafa ,  Paul J. Reuter ,  Yu Huang ,  Sudhakar Mannapuram Reddy

    IPC分类号： G01R31/3193 ,  G01R31/28

    CPC分类号： G01R31/3193

    摘要： Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.

    摘要翻译： 描述了用于调度嵌入在集成电路中的多个核的并发测试的方法。 通过将问题解决为二进制包装问题并使用修改后的二维或三维二进制包装启发式来进行测试调度。 多个核心的测试表示为至少用于测试核心和核心测试时间的集成电路引脚的功能。 表示可以包括测试核心所需的峰值功率的第三维度。 测试计划表示为具有至少集成电路引脚和集成电路测试时间的尺寸的存储区。 箱可以包括峰值功率的第三维度。 多核的调度是通过将多个核心测试表示拟合到bin来实现的。

    Reduced-pin-count-testing architectures for applying test patterns
    9.
    发明申请
    Reduced-pin-count-testing architectures for applying test patterns 有权
    用于应用测试模式的减少针数测试架构

    公开(公告)号：US20070011542A1

    公开(公告)日：2007-01-11

    申请号：US11305849

    申请日：2005-12-16

    申请人： Nilanjan Mukherjee ,  Jay Jahangiri ,  Ronald Press ,  Wu-Tung Cheng

    发明人： Nilanjan Mukherjee ,  Jay Jahangiri ,  Ronald Press ,  Wu-Tung Cheng

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G01R31/318541 ,  G01R31/318572 ,  G01R31/318583

    摘要： Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.

    摘要翻译： 公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。 方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。 例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。 电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。 在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到与用于控制电路的一个或多个内部扫描链的测试控制信号相对应的一个或多个边界扫描单元 测试中测试。 该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。

    Unified fabric port
    10.
    发明授权
    Unified fabric port 有权

    公开(公告)号：US09787608B2

    公开(公告)日：2017-10-10

    申请号：US13276966

    申请日：2011-10-19

    申请人： Jayakrishna Kidambi ,  Nilanjan Mukherjee ,  Vijoy Pandey

    发明人： Jayakrishna Kidambi ,  Nilanjan Mukherjee ,  Vijoy Pandey

    IPC分类号： H04L12/28 ,  H04L12/931 ,  H04L12/935

    CPC分类号： H04L49/351 ,  H04L49/3054 ,  H04L49/70

    摘要： A method and system for configuring communications over a physical communication link connected between a physical port of a network switch and a physical port of a physical network interface on an end station. The communication link between the physical port of the network switch and the physical port of the physical network interface is logically partitioned into a number of channels of communication. For each channel, a channel profile is generated that defines properties of that channel. The physical network interface is instructed to self-configure such that the physical network interface is able to communicate with the network switch over each channel in accordance with the channel profile defined for that channel.