公开(公告)号：US20070260926A1

公开(公告)日：2007-11-08

申请号：US11279609

申请日：2006-04-13

申请人： Donato Forlenza ,  Orazio Forlenza ,  Mary Kusko

发明人： Donato Forlenza ,  Orazio Forlenza ,  Mary Kusko

IPC分类号： G06F11/00

CPC分类号： G06F11/261

摘要： Exemplary embodiments include a static and dynamic test generation and simulation method including: analyzing a logic model; identifying a logic structure in the logic model whose input/output signal can be assigned to a particular logical value and remain fixed during a fault simulation test; and running the fault simulation test to check the logic model for faults.

摘要翻译： 示例性实施例包括静态和动态测试生成和仿真方法，包括：分析逻辑模型; 识别逻辑模型中的逻辑结构，其输入/输出信号可以被分配给特定的逻辑值并且在故障模拟测试期间保持固定; 并运行故障模拟测试，检查故障逻辑模型。

公开(公告)号：US20070011523A1

公开(公告)日：2007-01-11

申请号：US11149483

申请日：2005-06-09

申请人： Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Phong Tran

发明人： Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Phong Tran

IPC分类号： G01R31/28

CPC分类号： G06F11/2215

摘要： A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.

摘要翻译： 提供了实现扫描链诊断技术的方法，装置和计算机程序产品。 诊断技术包括使用耦合到扫描链的锁存器的熔丝将已知逻辑值加载到扫描链的已知位置处的锁存器中，然后从扫描链中卸载值，并且如果扫描链有缺陷（例如， 基于卸载的逻辑值），然后通过与已加载逻辑值的扫描链中的缺陷通过经由保险丝加载了已知逻辑值的扫描链的锁存器的已知位置进行比较来定位扫描链中的缺陷。 可以使用每n个锁存器在链上周期性间隔的保险丝对扫描链进行预先设计，以便于扫描链中检测到的缺陷的随后定位。

公开(公告)号：US20050229057A1

公开(公告)日：2005-10-13

申请号：US10821160

申请日：2004-04-08

申请人： Adrian Anderson ,  Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Phong Tran

发明人： Adrian Anderson ,  Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Phong Tran

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318569 ,  G01R31/318583 ,  G01R31/318591

摘要： A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.

摘要翻译： 提供了一种用于实现基于确定性的断层扫描链诊断的方法，装置和计算机程序产品。 生成确定性测试模式，并通过应用系统时钟的系统数据端口使用横向插入将其加载到被测设备中的每个扫描链中。 然后每个扫描链都被卸载，并且识别出最后一个切换锁存器。 测试步骤重复选定次数。 然后检查一致的结果。 当确定一致的结果时，所识别的最后一个切换锁存器被发送到物理故障分析系统。

公开(公告)号：US20050160339A1

公开(公告)日：2005-07-21

申请号：US10757781

申请日：2004-01-15

申请人： Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Bryan Robbins

发明人： Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Bryan Robbins

IPC分类号： G01R31/28 ,  G01R31/3183

CPC分类号： G01R31/318371 ,  G01R31/318342

摘要： Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Rather than store the entire set of test parameters for each of a plurality of test sequences to be performed, as with conventional test systems, embodiments of the present invention only store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.

摘要翻译： 提供了用于减少与内置自检（BIST）测试方法（例如，逻辑BIST，阵列BIST等）和模式结构相关联的测试数据量的方法和系统。 与常规测试系统一样，本发明的实施例不仅存储用于要执行的多个测试序列中的每一个的整个测试参数集合，而且存储针对已经改变的每个测试序列的有限数量的“动态”测试参数 相对于先前的测试序列。

公开(公告)号：US20050138514A1

公开(公告)日：2005-06-23

申请号：US10728348

申请日：2003-12-04

申请人： Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Steven Michnowski ,  James Webb

发明人： Todd Burdine ,  Donato Forlenza ,  Orazio Forlenza ,  William Hurley ,  Steven Michnowski ,  James Webb

IPC分类号： G01R31/3185 ,  G11B5/00 ,  G01R31/28 ,  G06K5/04 ,  G11B20/20

CPC分类号： G01R31/318569

摘要： An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.

摘要翻译： 一种装置，程序产品和方法利用在集成电路装置上提供的ABIST电路来帮助识别和定位也在集成电路装置上提供的扫描链中的缺陷。 特别地，可以通过将多个图案组应用于耦合到ABIST电路的扫描链来检测扫描链中的缺陷，从而将由多个图案组应用的结果生成的数据收集到扫描链中 并且使用所收集的扫描数据来识别扫描链中的有缺陷的锁存器。

公开(公告)号：US07017095B2

公开(公告)日：2006-03-21

申请号：US10064398

申请日：2002-07-10

申请人： Donato Forlenza ,  Franco Motika ,  Phillip J. Nigh

发明人： Donato Forlenza ,  Franco Motika ,  Phillip J. Nigh

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318586 ,  G01R31/318544

摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

摘要翻译： 通过组合确定性和功能测试，通过确定故障电路中的错误的位置和类型，基于功能故障来创建新的测试模式来诊断半导体器件功能测试故障的方法。 这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用 生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

公开(公告)号：US07574644B2

公开(公告)日：2009-08-11

申请号：US11166019

申请日：2005-06-25

申请人： Donato Forlenza ,  Franco Molika ,  Phillip J. Nigh

发明人： Donato Forlenza ,  Franco Molika ,  Phillip J. Nigh

IPC分类号： G06F11/00

CPC分类号： G01R31/318586 ,  G01R31/318544

摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

摘要翻译： 一种诊断半导体器件功能测试故障的方法，通过组合确定性和功能测试，通过确定故障电路中错误类型的位置，基于功能故障创建新的测试模式。 这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用 生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

公开(公告)号：US20050289426A1

公开(公告)日：2005-12-29

申请号：US11166019

申请日：2005-06-25

申请人： Donato Forlenza ,  Franco Molika ,  Phillip Nigh

发明人： Donato Forlenza ,  Franco Molika ,  Phillip Nigh

IPC分类号： G01R31/3185 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318586 ,  G01R31/318544

摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

摘要翻译： 一种诊断半导体器件功能测试故障的方法，通过组合确定性和功能测试，通过确定故障电路中错误类型的位置，基于功能故障创建新的测试模式。 这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用 生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。