公开(公告)号：US20160049423A1

公开(公告)日：2016-02-18

申请号：US14695249

申请日：2015-04-24

申请人： Dongchul YOO ,  Chaeho KIM ,  Jaeyoung AHN ,  Woong LEE

发明人： Dongchul YOO ,  Chaeho KIM ,  Jaeyoung AHN ,  Woong LEE

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

摘要翻译： 三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道 穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案 通道孔，但不在虚拟孔中。

公开(公告)号：US20160365357A1

公开(公告)日：2016-12-15

申请号：US15250091

申请日：2016-08-29

申请人： Chaeho KIM ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

发明人： Chaeho KIM ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

IPC分类号： H01L27/115 ,  H01L29/51 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42348 ,  H01L29/513

摘要： A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

公开(公告)号：US20160225785A1

公开(公告)日：2016-08-04

申请号：US14960776

申请日：2015-12-07

申请人： Chaeho KIM ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

发明人： Chaeho KIM ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42348 ,  H01L29/513

摘要： A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

摘要翻译： 一种半导体存储器件包括：堆叠，其包括交替重复堆叠在衬底上的栅电极和绝缘层。 细胞通道结构穿透堆叠。 单元沟道结构包括与基板接触的第一半导体图案和第一半导体图案上的第一沟道图案。 第一半导体图案延伸到从基板的表面到第一半导体图案的顶表面的第一高度。 衬底上的虚拟通道结构，与堆叠间隔开。 虚设通道结构包括接触衬底的第二半导体图案和第二半导体图案上的第二沟道图案。 第二半导体图案延伸到从基板的表面到第二半导体图案的顶表面的第二高度。 第一个高度大于第二个高度。