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    Nonvolatile memory devices and methods of fabricating the same
    2.
    发明授权
    Nonvolatile memory devices and methods of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US09490371B2

    公开(公告)日：2016-11-08

    申请号：US14539043

    申请日：2014-11-12

    申请人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    发明人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/115

    CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

    摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

    摘要翻译： 非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储 垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。 电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。 第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160049423A1

    公开(公告)日：2016-02-18

    申请号：US14695249

    申请日：2015-04-24

    申请人： Dongchul YOO ,  Chaeho KIM ,  Jaeyoung AHN ,  Woong LEE

    发明人： Dongchul YOO ,  Chaeho KIM ,  Jaeyoung AHN ,  Woong LEE

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

    摘要翻译： 三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道 穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案 通道孔，但不在虚拟孔中。

    Nonvolatile Memory Devices And Methods Of Fabricating The Same
    4.
    发明申请
    Nonvolatile Memory Devices And Methods Of Fabricating The Same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20150194440A1

    公开(公告)日：2015-07-09

    申请号：US14539043

    申请日：2014-11-12

    申请人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    发明人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    IPC分类号： H01L27/115 ,  H01L29/792

    CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

    摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

    摘要翻译： 非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储 垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。 电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。 第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

    Nonvolatile Memory Devices And Methods Of Manufacturing The Same
    8.
    发明申请
    Nonvolatile Memory Devices And Methods Of Manufacturing The Same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20120104485A1

    公开(公告)日：2012-05-03

    申请号：US13281784

    申请日：2011-10-26

    申请人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

    发明人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L27/11568

    摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.

    摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上依次形成隧道介电层，电荷存储层和硬掩模层。 通过在衬底中形成沟槽来限定活性部分。 通过对硬掩模层，电荷存储层，隧道介电层和衬底进行顺序构图，按顺序在有源部分的每一个上形成隧道电介质图案，初电电荷存储图案和硬掩模图案。 形成覆盖沟槽的上表面的覆盖图案，使得第一空隙保留在沟槽的下部，封盖图案包括通过溅射蚀刻工艺蚀刻硬掩模图案形成的蚀刻颗粒。

    Semiconductor device and method of fabricating the same
    9.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09536897B2

    公开(公告)日：2017-01-03

    申请号：US14695249

    申请日：2015-04-24

    申请人： Dongchul Yoo ,  Chaeho Kim ,  Jaeyoung Ahn ,  Woong Lee

    发明人： Dongchul Yoo ,  Chaeho Kim ,  Jaeyoung Ahn ,  Woong Lee

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

    摘要翻译： 三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道 穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案 通道孔，但不在虚拟孔中。