利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3 条记录 (耗时 0.026 秒)

    Static memory having pipeline registers
    2.
    发明授权
    Static memory having pipeline registers 失效
    具有管道寄存器的静态记忆

    公开(公告)号：US5093809A

    公开(公告)日：1992-03-03

    申请号：US487932

    申请日：1990-03-05

    申请人： Doris Schmitt-Landsiedel ,  Bernhard Hoppe ,  Gerd Neuendorf ,  Maria Wurm

    发明人： Doris Schmitt-Landsiedel ,  Bernhard Hoppe ,  Gerd Neuendorf ,  Maria Wurm

    IPC分类号： G11C11/413 ,  G11C5/02 ,  G11C11/41 ,  G11C11/419

    CPC分类号： G11C5/025 ,  G11C11/41 ,  G11C11/419

    摘要： Static memory having pipeline registers. The static memory has a plurality of hierarchy levels connected by pipeline registers. This architecture is very beneficial since the area requirements for the drive and read-out circuits in the first hierarchy level are especially critical. Advantageously, memory cells are used which have write and read word lines as well as separate write and read data lines and which also supply a strong cell signal so that only a few components are needed for the read circuit. A new clock format with an arrangement of pipeline registers is proposed for the appertaining memory for which power consumption is reduced by disconnecting the clocks in the lower hierarchy levels, resulting in increased area savings.

    摘要翻译： 具有流水线寄存器的静态存储器。 静态存储器具有通过流水线寄存器连接的多个层级。 这种架构是非常有益的，因为第一层次驱动器和读出电路的面积要求尤其重要。 有利地，使用具有写入和读取字线以及单独的写入和读取数据线并且还提供强电池信号以使得读取电路仅需要少量组件的存储器单元。 提出了一种具有流水线寄存器布置的新时钟格式，用于通过断开较低层次级别的时钟来降低功耗的存储器，从而增加了面积节省。

    Static memory cell
    3.
    发明授权
    Static memory cell 失效
    静态存储单元

    公开(公告)号：US5040146A

    公开(公告)日：1991-08-13

    申请号：US491201

    申请日：1990-03-09

    申请人： Hans-Juergen Mattausch ,  Bernhard Hoppe ,  Gerd Neuendorf ,  Doris Schmitt-Landsiedel ,  Hans-Joerg Pfleiderer ,  Maria Wurm

    发明人： Hans-Juergen Mattausch ,  Bernhard Hoppe ,  Gerd Neuendorf ,  Doris Schmitt-Landsiedel ,  Hans-Joerg Pfleiderer ,  Maria Wurm

    IPC分类号： G11C8/16 ,  G11C11/412

    CPC分类号： G11C8/16 ,  G11C11/412

    摘要： Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.

    摘要翻译： 公开了存储器单元，当它们被用于静态存储器模块中时，避免在存储器外围电路中利用模拟电路，并且旨在在面临技术修改和参数波动时提高干扰的可靠性。 通过写入选择晶体管从写入数据线发生写入，并且通过读取选择晶体管将读出发生到读取数据线上。 由两个场效应晶体管形成的第二反相器用作反馈元件，以便静态地维持单元信息。 由于在第一和第二逆变器之间的尺寸确定方面的不对称性，当与先前已知的存储器单元相比时，存储器单元在读出时显着地较不易于信息丢失。 这些存储单元不需要读取数据线的预充电。