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1.发明授权公开(公告)号：US07806853B2
公开(公告)日：2010-10-05
申请号：US12471150
申请日：2009-05-22
IPC分类号： A61M31/00
CPC分类号： A61M5/1723 , A61B5/14532 , A61M5/14244 , A61M2230/201 , A61M2230/62 , G06F19/00
摘要： The invention concerns an array and a method for dosing a hormone regulating the blood glucose, especially insulin, of a diabetic patient. In order to improve the administration of the hormone, the invention provides the following characteristic combination: a first sensor for measuring tissue glucose level; a controller having as an input the measured tissue glucose level from the first sensor, the controller having a control algorithm to determine an amount of hormone to be dosed based upon the measured tissue glucose level; a hormone dosing unit connected to the controller and automatically administering a hormone dose based upon a signal received from the controller; a second sensor for measuring an influencing patient variable; a pilot control device connected to the second sensor, the pilot control device connected to and forming a circuit with the controller, the pilot control device acting on the controller in accordance with the influencing patient variable that is measured by the second sensor, whereby the pilot control device reduces dead time of the controller.
摘要翻译： 本发明涉及用于给予调节糖尿病患者的血糖，特别是胰岛素的激素的阵列和方法。 为了改善激素的施用，本发明提供以下特征组合：用于测量组织葡萄糖水平的第一传感器; 控制器具有来自第一传感器的测量的组织葡萄糖水平作为输入，控制器具有控制算法，用于基于所测量的组织葡萄糖水平来确定要给药的激素的量; 激素计量单元，其连接到所述控制器并基于从所述控制器接收的信号自动施用激素剂量; 用于测量影响患者变量的第二传感器; 连接到所述第二传感器的先导控制装置，所述先导控制装置与所述控制器连接并与所述控制器形成电路，所述先导控制装置根据由所述第二传感器测量的影响的患者变量作用在所述控制器上， 控制装置减少控制器的死区时间。
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2.发明申请公开(公告)号：US20090254024A1
公开(公告)日：2009-10-08
申请号：US12471150
申请日：2009-05-22
IPC分类号： A61M37/00
CPC分类号： A61M5/1723 , A61B5/14532 , A61M5/14244 , A61M2230/201 , A61M2230/62 , G06F19/00
摘要： The invention concerns an array and a method for dosing a hormone regulating the blood glucose, especially insulin, of a diabetic patient (10). In order to improve the administration of the hormone, the invention provides the following characteristic combination: a) a measuring device (16) to detect measured values correlatable with blood sugar; b) a controlling means (12) comprising a controller (44) and a hormone dosing device (46) for supplying a hormone dosage; c) a pilot control device (14) acting on the hormone fine dosage controlling means (12) for performing a coarse pre-control in accordance with at least one influence variable that influences blood glucose.
摘要翻译： 本发明涉及用于给予调节糖尿病患者的血糖特别是胰岛素的激素的阵列和方法（10）。 为了改善激素的施用，本发明提供以下特征组合：a）检测与血糖相关的测量值的测量装置（16）; b）包括用于提供激素剂量的控制器（44）和激素计量装置（46）的控制装置（12） c）作用于激素精细剂量控制装置（12）的先导控制装置（14），用于根据影响血糖的至少一个影响变量执行粗略预控制。
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公开(公告)号：US5276773A
公开(公告)日：1994-01-04
申请号：US374745
申请日：1989-07-03
CPC分类号： G06N3/063
摘要： A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E). Individual processing outputs of the evaluators (B) are connected to individual processing inputs of the decision unit (E) in the appertaining neuron (N), so that every output information (INF.sub.A) can be indirectly fed back onto every neuron (NR).
摘要翻译： 数字神经网络具有彼此完全啮合的多个神经元（NR），每个神经元（NR）包括评估阶段，其具有与多个神经元（NR）数目相等的多个评估器（B），其中每个 包括具有决定单元（E）的判定阶段。 可以通过预处理装置经由信息输入向每个判定单元（E）提供影响决定单元（E）的定义的预调整的调整信息（INFE）。 加密信息（INFG）可以通过预处理装置经由个人信息输入提供给每个评估者（B）。 输出信息（INFA）可以由每个决定单元（E）通过相应的个人信息输出输出到后处理装置。 决策单元（E）的信息输出各自连接到分配给独立决定单元（E）的所有评估者（B）的单独处理输入。 评估器（B）的单独处理输出连接到独立神经元（N）中的决策单元（E）的各个处理输入，使得每个输出信息（INFA）可被间接反馈到每个神经元（NR）。
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公开(公告)号：US4843341A
公开(公告)日：1989-06-27
申请号：US137606
申请日：1987-12-24
CPC分类号： H03F3/45179 , H03F1/0261 , H03F3/45076 , H03F2203/45112 , H03F2203/45192 , H03F2203/45281 , H03F2203/45466 , H03F2203/45471
摘要： The differential amplifier has two n-channel or p-channel field effect transistors serving as controllable current sources which supply auxiliary currents upon appearance of an input signal which amplify the quiescent current. The inputs of the differential amplifier are connected to the gate terminals of the n-channel or p-channel field effect transistors via a level-converting circuit for converting the d.c. component of the input signal superimposed on a gate bias voltage to a lower or, respectively, higher output level. As a result of the control of the current sources proceeding from the amplifier input good driver qualities, a distortion-free signal transmission and a lower dissipation power are guaranteed.
摘要翻译： 差分放大器具有两个n沟道或p沟道场效应晶体管，用作可控电流源，在出现放大静态电流的输入信号时，提供辅助电流。 差分放大器的输入通过电平转换电路连接到n沟道或p沟道场效应晶体管的栅极端，用于转换直流电场。 叠加在栅极偏置电压上的输入信号的分量变为较低的或分别较高的输出电平。 由于控制来自放大器输入的电流源的良好驱动器质量的结果，可以保证无失真的信号传输和较低的耗散功率。
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公开(公告)号：US4760035A
公开(公告)日：1988-07-26
申请号：US942023
申请日：1986-12-12
IPC分类号： H01L27/06 , H01L21/285 , H01L27/07 , H01L27/08 , H01L27/092 , H01L21/425
CPC分类号： H01L21/28518 , H01L27/0727 , H01L27/0925
摘要： An integrated circuit in complementary circuit technology comprising two field effect transistors (T1, T2) of different channel types with the first one (T2) mounted in a doped semiconductor body (1) having a first conductivity type and the other FET (T1) mounted in a semiconductor zone 2 of a second conductivity type which is arranged in said body. The object is to provide a protection against thermal overloads which can appear due to "latch up" influences when overvoltages at the one connecting region of the field effect transistor (T1) mounted in the semiconductor zone occur. This is accomplished by the mounting of a metal contact (12) on the surface of a semiconductor region (2') inserted into the semiconductor body 1 and doped oppositely thereto with such metal contact forming a Schottky diode (D) with the semiconductor region (2') which can be connected to the connecting region of the field effect transistor T1 mounted in the semiconductor region 2 whereas the semiconductor region (2') is electrically connected to the supply voltage (V.sub.DD). The circuits are applied in CMOS circuits.
摘要翻译： 一种互补电路技术的集成电路，包括具有不同通道类型的两个场效应晶体管（T1，T2），第一个（T2）安装在具有第一导电类型的掺杂半导体本体（1）中，另一个FET（T1）安装 在布置在所述主体中的第二导电类型的半导体区域2中。 本发明的目的是提供一种防止由于安装在半导体区域中的场效应晶体管（T1）的一个连接区域处的过电压而引起的“闭锁”影响而可能出现的热过载的保护。 这是通过在插入半导体本体1的半导体区域（2'）的表面上安装金属接触（12）并且与其相反地掺杂的金属接触（其形成肖特基二极管（D））与半导体区域（ 2'），其可以连接到安装在半导体区域2中的场效应晶体管T1的连接区域，而半导体区域（2'）电连接到电源电压（VDD）。 这些电路应用于CMOS电路中。
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公开(公告)号：US4358786A
公开(公告)日：1982-11-09
申请号：US57128
申请日：1979-07-11
CPC分类号： H04N9/7973 , H04N5/919
摘要： Video signals are stored on a continuously movable magnetic tape with a dissection of the video signals into a plurality of partial signals and simultaneously recording the partial signals in a plurality of longitudinal tracks which extend parallel to one another. Inasmuch as mutual influences of the individual image formation to be stored are to be reduced, even given a great recording density, the signal lines of the video signal are employed as partial signals, whereby the line signals belonging to a television image are combined to at least one group and are successively recorded in groups. All line signals belonging to one and the same group are simultaneously recorded on a plurality of longitudinal tracks after an intermediate storage. The invention finds particular application in video recorders having longitudinal track recording.
摘要翻译： 将视频信号存储在具有将视频信号解剖为多个部分信号的可连续移动的磁带上，同时将部分信号记录在彼此平行延伸的多个纵向磁道中。 为了减少要存储的各个图像形成的相互影响，即使给定较大的记录密度，视频信号的信号线被用作部分信号，由此将属于电视图像的线信号组合到 至少一组，并连续记录在一起。 属于同一组的所有线信号在中间存储之后同时记录在多个纵向轨道上。 本发明特别适用于具有纵向记录的录像机。
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7.发明授权Transversal filter with at least one analogue shift register, and process for the operation thereof 失效具有至少一个模拟移位寄存器的横向滤波器及其操作的处理
公开(公告)号：US4163957A
公开(公告)日：1979-08-07
申请号：US832232
申请日：1977-09-12
CPC分类号： H03H15/02 , H01L29/76891 , H03H15/023
摘要： In illustrated embodiments, at least one analogue shift register has a number of parallel inputs and one series output. A number of individual evaluating circuits receive the signal to be filtered and supply respective output quantities of charge equal to the product of the difference between the relevant signal value and a predetermined minimum or maximum value, and a respective individual evaluation factor. The output of each evaluating circuit can be connected via a switching element to an associated parallel input. The capacity of every storage position of the shift register is at least such that it is always able to accommodate the maximum quantity of charge supplied by the preceding storage position, and when the storage position has a parallel input, can additionally accommodate the maximum quantities of charge supplied by the associated evaluating circuit (s). Various modifications are disclosed for reducing the space requirement of a transversal filter when implemented, for example, as a CCD.
摘要翻译： 在所示实施例中，至少一个模拟移位寄存器具有多个并行输入和一个串联输出。 多个单独的评估电路接收要滤波的信号，并提供相应的输出电荷量等于相关信号值与预定最小值或最大值之差的乘积，以及各自的评估因子。 每个评估电路的输出可以经由开关元件连接到相关联的并行输入。 移位寄存器的每个存储位置的容量至少使得其总是能够适应由先前存储位置提供的最大量的电荷，并且当存储位置具有并行输入时，可另外容纳最大量的 由相关联的评估电路提供的电荷。 公开了用于在实现例如CCD时减小横向滤波器的空间需求的各种修改。
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公开(公告)号：US4064491A
公开(公告)日：1977-12-20
申请号：US723312
申请日：1976-09-15
申请人： Karl Knauer , Hans Joerg Pfleiderer
发明人： Karl Knauer , Hans Joerg Pfleiderer
IPC分类号： G11C11/404 , H01L27/108 , H01L27/12 , H01L29/10 , H01L29/423 , H01L29/94 , G11C11/24
CPC分类号： G11C11/404 , H01L27/10805 , H01L27/12 , H01L29/1062 , H01L29/42396 , H01L29/94
摘要： An information memory for storing information in the form of electric charge carriers has at least one dynamic storage element which is arranged upon a surface of at least one substrate made of semiconductor material and doped with a given basic type doping. The substrate connection is included and the memory comprises at least one MIS capacitor. Upon the substrate surface at least one electrically insulating layer is present which carries at least one capacitor electrode. The dynamic storage element comprises the MIS capacitor or an adjacent arrangement of several MIS capacitors, separated from one another by, at the most, narrow distances and comprises at least one contact area at the substrate surface which is provided with an externally accessible ohmic terminal contact, and which contacts at least the margin of the MIS capacitor or t least one of the MIS capacitors, nd which contains material having the basic type of doping. Within the electrically insulating layer, within the MIS capacitor or capacitors, the values of the numerical ratio .epsilon./d--whereby .epsilon. is the dielectric constant and d is the layer thickness of the electrically insulating layer--and/or the values of the surface density of the basic type of doping of the substrate in the area or in the areas of the MIS capacitor or capacitors and/or the values of the surface density, with respect to the surface of the substrate, of and adjacent to the substrate and doped opposite to the type of doping of the substrate layer, are selected differently with respect to location in such a way that, by the way of applying an electrode voltage, which may be given within a wide range between the substrate terminal and electrode, the local distribution of the amounts of the potential maximum between the range or within the ranges of the MIS capacitor or capacitor, comprises, laterally away from the contact area beginning at the side of the contact area, at least one increase from a minimum value to a maximum value.
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公开(公告)号：US5040146A
公开(公告)日：1991-08-13
申请号：US491201
申请日：1990-03-09
申请人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
发明人： Hans-Juergen Mattausch , Bernhard Hoppe , Gerd Neuendorf , Doris Schmitt-Landsiedel , Hans-Joerg Pfleiderer , Maria Wurm
IPC分类号： G11C8/16 , G11C11/412
CPC分类号： G11C8/16 , G11C11/412
摘要： Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.
摘要翻译： 公开了存储器单元，当它们被用于静态存储器模块中时，避免在存储器外围电路中利用模拟电路，并且旨在在面临技术修改和参数波动时提高干扰的可靠性。 通过写入选择晶体管从写入数据线发生写入，并且通过读取选择晶体管将读出发生到读取数据线上。 由两个场效应晶体管形成的第二反相器用作反馈元件，以便静态地维持单元信息。 由于在第一和第二逆变器之间的尺寸确定方面的不对称性，当与先前已知的存储器单元相比时，存储器单元在读出时显着地较不易于信息丢失。 这些存储单元不需要读取数据线的预充电。
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10.发明授权Method and arrangement for an operational check of a programmable logic array 失效用于可编程逻辑阵列的操作检查的方法和装置
公开(公告)号：US4517672A
公开(公告)日：1985-05-14
申请号：US401229
申请日：1982-07-23
IPC分类号： G06F11/22 , G01R31/3185 , H03K19/177 , G06F11/00
CPC分类号： G01R31/318516
摘要： A function check of a programmable logic array is performed in which input lines, product term lines and ground lines are combined into an AND plane and output lines, product term lines and ground lines are combined into an OR plane. The aim is a simple method of function check which permits any potentially-existing fault to be detected. The check is achieved by generating, with a test data generator, bit patterns and applying the same to the input lines, and, through the use of a shift register, successively sensitizing the product term lines either individually or in groups, i.e. disconnecting the same from ground potential. The bit patterns occurring at the output lines are supplied to a test data evaluator. The area of use is in logic circuitry of data processing technology.
摘要翻译： 执行可编程逻辑阵列的功能检查，其中将输入线，乘积项线和接地线组合成AND平面，并将输出线，乘积项线和接地线组合成OR平面。 目的是一种简单的功能检查方法，可以检测任何潜在的故障。 通过使用测试数据发生器生成位模式并将其应用于输入线路来实现该检查，并且通过使用移位寄存器，对产品项目线路单独或分组地依次敏感化，即断开相同的 从地电位。 在输出线上发生的位模式被提供给测试数据评估器。 使用的领域是数据处理技术的逻辑电路。
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